Patchwork [v2,07/10] target-arm: optimize thumb2 load/store multiple ops

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Submitter Juha.Riihimaki@nokia.com
Date Oct. 24, 2009, 12:19 p.m.
Message ID <1256386749-85299-8-git-send-email-juha.riihimaki@nokia.com>
Download mbox | patch
Permalink /patch/36835/
State New
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Comments

Juha.Riihimaki@nokia.com - Oct. 24, 2009, 12:19 p.m.
From: Juha Riihimäki <juha.riihimaki@nokia.com>

Thumb2 load/store multiple instructions can be slightly optimized by
loading the register offset constant into a variable outside the
register loop and using the preloaded variable inside the loop instead
of reloading the offset value to a temporary variable on each loop
iteration. This causes less TCG ops to be generated for a Thumb2 load/
store multiple instruction if there are more than one register
accessed, otherwise the amount of generated TCG ops will be the same.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
---
 target-arm/translate.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)
Laurent Desnogues - Oct. 24, 2009, 5:32 p.m.
On Sat, Oct 24, 2009 at 2:19 PM,  <juha.riihimaki@nokia.com> wrote:
> From: Juha Riihimäki <juha.riihimaki@nokia.com>
>
> Thumb2 load/store multiple instructions can be slightly optimized by
> loading the register offset constant into a variable outside the
> register loop and using the preloaded variable inside the loop instead
> of reloading the offset value to a temporary variable on each loop
> iteration. This causes less TCG ops to be generated for a Thumb2 load/
> store multiple instruction if there are more than one register
> accessed, otherwise the amount of generated TCG ops will be the same.
>
> Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>

Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>


Laurent

> ---
>  target-arm/translate.c |    4 +++-
>  1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 9e924d4..353f638 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -7374,6 +7374,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
>                     tcg_gen_addi_i32(addr, addr, -offset);
>                 }
>
> +                tmp2 = tcg_const_i32(4);
>                 for (i = 0; i < 16; i++) {
>                     if ((insn & (1 << i)) == 0)
>                         continue;
> @@ -7390,8 +7391,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
>                         tmp = load_reg(s, i);
>                         gen_st32(tmp, addr, IS_USER(s));
>                     }
> -                    tcg_gen_addi_i32(addr, addr, 4);
> +                    tcg_gen_add_i32(addr, addr, tmp2);
>                 }
> +                tcg_temp_free_i32(tmp2);
>                 if (insn & (1 << 21)) {
>                     /* Base register writeback.  */
>                     if (insn & (1 << 24)) {
> --
> 1.6.5
>
>
>
>

Patch

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9e924d4..353f638 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7374,6 +7374,7 @@  static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
                     tcg_gen_addi_i32(addr, addr, -offset);
                 }
 
+                tmp2 = tcg_const_i32(4);
                 for (i = 0; i < 16; i++) {
                     if ((insn & (1 << i)) == 0)
                         continue;
@@ -7390,8 +7391,9 @@  static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
                         tmp = load_reg(s, i);
                         gen_st32(tmp, addr, IS_USER(s));
                     }
-                    tcg_gen_addi_i32(addr, addr, 4);
+                    tcg_gen_add_i32(addr, addr, tmp2);
                 }
+                tcg_temp_free_i32(tmp2);
                 if (insn & (1 << 21)) {
                     /* Base register writeback.  */
                     if (insn & (1 << 24)) {