From patchwork Mon Jul 7 14:33:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 367590 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 699A41400B9 for ; Tue, 8 Jul 2014 00:34:10 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type; q=dns; s=default; b=XbYIzUkTl2JmVw1p 7bl+cnGIry5kBZqiIw5aWMaPujqvfifs6HVlyVZ/i7Ry60J9uf6hzV/V2V08R1Qo 8qSji4fPYdo8fEUIx7n6RTDCBUuS+QArKbqSxUZf/dxLFr+t5ooT10IjLo+XIKwy IK1hkO2cPF2AGWVQ3hOJ8jdyVJM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type; s=default; bh=yWDqgyeNoc18T79IQOHFjy qcetA=; b=J6v8en6IgUZzbQkRVicTQ3txgaQi5znc09kck9HqnvRC7Q8/ylJa2P JxKtES1WirlOBcjZCww9RnxmjYBgpXdAINngpaxinm3NGP7rNiY0RCZ+kOqw4bGA F0UqWQnniHnTAkPW1KUzEAnAF7dPMfHtR4pT7RpDJ9ctAmEKcWTUQ= Received: (qmail 10508 invoked by alias); 7 Jul 2014 14:33:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 10349 invoked by uid 89); 7 Jul 2014 14:33:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 07 Jul 2014 14:33:39 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1X49z3-00003l-Pq from Maciej_Rozycki@mentor.com ; Mon, 07 Jul 2014 07:33:33 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 7 Jul 2014 07:33:33 -0700 Received: from localhost (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server (TLS) id 14.2.247.3; Mon, 7 Jul 2014 15:33:32 +0100 Date: Mon, 7 Jul 2014 15:33:26 +0100 From: "Maciej W. Rozycki" To: David Edelsohn CC: GCC Patches Subject: Re: [PATCH] Power/GCC: Implement little-endian SPE operations In-Reply-To: Message-ID: References: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 On Mon, 7 Jul 2014, David Edelsohn wrote: > gcc/ > * config/rs6000/rs6000.c (output_vec_const_move): Handle > little-endian code generation. > * config/rs6000/spe.md (spe_evmergehi): Rename to... > (vec_perm00_v2si): ... this. Handle little-endian code > generation. > (spe_evmergehilo): Rename to... > (vec_perm01_v2si): ... this. Handle little-endian code > generation. > (spe_evmergelo): Rename to... > (vec_perm11_v2si): ... this. Handle little-endian code > generation. > (spe_evmergelohi): Rename to... > (vec_perm10_v2si): ... this. Handle little-endian code > generation. > (spe_evmergehi, spe_evmergehilo): New expanders. > (spe_evmergelo, spe_evmergelohi): Likewise. > (*frob__): Handle little-endian code > generation. > (*frob_tf_ti): Likewise. > (*frob__di_2): Likewise. > (*frob_tf_di_8_2): Likewise. > (*frob_di_): Likewise. > (*frob_ti_tf): Likewise. > (*frob___2): Likewise. > (*frob_ti__8_2): Likewise. > (*frob_ti_tf_2): Likewise. > (mov_si_e500_subreg0): Rename to... > (mov_si_e500_subreg0_be): ... this. Restrict to the big > endianness only. > (*mov_si_e500_subreg0_le): New instruction pattern. > (*mov_si_e500_subreg0_elf_low): Rename to... > (*mov_si_e500_subreg0_elf_low_be): ... this. Restrict to > the big endianness only. > (*mov_si_e500_subreg0_elf_low_le): New instruction pattern. > (*mov_si_e500_subreg0_2): Rename to... > (*mov_si_e500_subreg0_2_be): ... this. Restrict to the > big big endianness only. > (*mov_si_e500_subreg0_2_le): New instruction pattern. > (*mov_si_e500_subreg4): Rename to... > (*mov_si_e500_subreg4_be): ... this. Restrict to the big > endianness only. > (mov_si_e500_subreg4_le): New instruction pattern. > (*mov_si_e500_subreg4_elf_low): Rename to... > (*mov_si_e500_subreg4_elf_low_be): ... this. Restrict to > the big endianness only. > (*mov_si_e500_subreg4_elf_low_le): New instruction/splitter > pattern. > (*mov_si_e500_subreg4_2): Rename to... > (*mov_si_e500_subreg4_2_be): ... this. Restrict to the big > endianness only. > (*mov_si_e500_subreg4_2_le): New instruction pattern. > (*mov_sitf_e500_subreg8): Rename to... > (*mov_sitf_e500_subreg8_be): ... this. Restrict to the big > endianness only. > (*mov_sitf_e500_subreg8_le): New instruction pattern. > (*mov_sitf_e500_subreg8_2): Rename to... > (*mov_sitf_e500_subreg8_2_be): ... this. Restrict to the big > endianness only. > (*mov_sitf_e500_subreg8_2_le): New instruction pattern. > (*mov_sitf_e500_subreg12): Rename to... > (*mov_sitf_e500_subreg12_be): ... this. Restrict to the big > endianness only. > (*mov_sitf_e500_subreg12_le): New instruction pattern. > (*mov_sitf_e500_subreg12_2): Rename to... > (*mov_sitf_e500_subreg12_2_be): ... this. Restrict to the big > endianness only. > (*mov_sitf_e500_subreg12_2_le): New instruction pattern. > > gcc/testsuite/ > * gcc.target/powerpc/spe-evmerge.c: New file. > > Okay. > > Could you add a short comment explaining what the "0" and "1" labels > in vec_perm[01][01]_v2si mean? Like this? Maciej gcc-ppc-spe-le-update.diff Index: gcc-fsf-trunk-quilt/gcc/config/rs6000/spe.md =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/rs6000/spe.md 2014-07-07 15:27:54.258937029 +0100 +++ gcc-fsf-trunk-quilt/gcc/config/rs6000/spe.md 2014-07-07 15:26:43.748937008 +0100 @@ -438,6 +438,11 @@ [(set_attr "type" "vecload") (set_attr "length" "4")]) +;; Integer vector permutation instructions. The pairs of digits in the +;; names of these instructions indicate the indices, in the memory vector +;; element ordering, of the vector elements permuted to the output vector +;; from the first and the second input vector respectively. + (define_insn "vec_perm00_v2si" [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") (vec_select:V2SI @@ -571,6 +576,8 @@ DONE; }) +;; End of integer vector permutation instructions. + (define_insn "spe_evnand" [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")