diff mbox

[U-Boot,v4,08/13] board: gdsys: Configure bridge on DP501 to support DDC only

Message ID 1404372506-15314-9-git-send-email-dirk.eibach@gdsys.cc
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Dirk Eibach July 3, 2014, 7:28 a.m. UTC 
From: Dirk Eibach <dirk.eibach@gdsys.cc>

The I2C bridge on DP501 supports EDID, MCCS and HDCP by default.
Allow EDID only to avoid I2C address conflicts.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/gdsys/common/dp501.c       | 1 +
 include/configs/controlcenterd.h | 7 ++++---
 2 files changed, 5 insertions(+), 3 deletions(-)

Comments

Tom Rini July 8, 2014, 1:39 a.m. UTC | #1 
On Thu, Jul 03, 2014 at 09:28:21AM +0200, Dirk Eibach wrote:

> From: Dirk Eibach <dirk.eibach@gdsys.cc>
> 
> The I2C bridge on DP501 supports EDID, MCCS and HDCP by default.
> Allow EDID only to avoid I2C address conflicts.
> 
> Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>

Applied to u-boot/master, thanks!
diff mbox

Patch

diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index e00e589..7958bae 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -54,6 +54,7 @@  static void dp501_link_training(u8 addr)
 void dp501_powerup(u8 addr)
 {
 	dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+	dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
 	i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
 	dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
 	dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 868813f..ec3145f 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -199,9 +199,10 @@ 
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-/* Probing DP501 I2C-Bridge will hang */
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x30}, {0, 0x37}, {0, 0x3a}, \
-					  {0, 0x3b}, {0, 0x50} }
+
+#ifndef CONFIG_TRAILBLAZER
+#define CONFIG_CMD_I2C
+#endif
 
 #define CONFIG_PCA9698			/* NXP PCA9698 */