| Message ID | 1404142497-6430-6-git-send-email-mihai.caraman@freescale.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
On 30.06.14 17:34, Mihai Caraman wrote: > Add ONE_REG support for AltiVec on Book3E. > > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Any chance we can handle these in generic code? Alex
> -----Original Message----- > From: Alexander Graf [mailto:agraf@suse.de] > Sent: Thursday, July 03, 2014 3:34 PM > To: Caraman Mihai Claudiu-B02008; kvm-ppc@vger.kernel.org > Cc: kvm@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > Subject: Re: [PATCH 5/6 v2] KVM: PPC: Book3E: Add ONE_REG AltiVec support > > > On 30.06.14 17:34, Mihai Caraman wrote: > > Add ONE_REG support for AltiVec on Book3E. > > > > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> > > Any chance we can handle these in generic code? I expected this request :) Can we let this for a second phase to have e6500 enabled first? Can you share with us a Book3S setup so I can validate the requested changes? I already fell anxious touching strange hardware specific Book3S code without running it. -Mike
On 03.07.14 18:11, mihai.caraman@freescale.com wrote: >> -----Original Message----- >> From: Alexander Graf [mailto:agraf@suse.de] >> Sent: Thursday, July 03, 2014 3:34 PM >> To: Caraman Mihai Claudiu-B02008; kvm-ppc@vger.kernel.org >> Cc: kvm@vger.kernel.org; linuxppc-dev@lists.ozlabs.org >> Subject: Re: [PATCH 5/6 v2] KVM: PPC: Book3E: Add ONE_REG AltiVec support >> >> >> On 30.06.14 17:34, Mihai Caraman wrote: >>> Add ONE_REG support for AltiVec on Book3E. >>> >>> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> >> Any chance we can handle these in generic code? > I expected this request :) Can we let this for a second phase to have > e6500 enabled first? I don't see the value of duplicating code in e500 specific code only to remove and combine it in common code in a follow-up patch after that. > Can you share with us a Book3S setup so I can validate the requested > changes? I already fell anxious touching strange hardware specific > Book3S code without running it. Until a few weeks ago I had an externally reachable G5 machine that we could've used for this. Unfortunately I had to replace the box with another one that's not quite as stable. I'll try and see if I can fix or replace it soon. Alex
diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h index 2bc4a94..3adbce4 100644 --- a/arch/powerpc/include/uapi/asm/kvm.h +++ b/arch/powerpc/include/uapi/asm/kvm.h @@ -476,6 +476,11 @@ struct kvm_get_htab_header { /* FP and vector status/control registers */ #define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80) +/* + * VSCR register is documented as a 32-bit register in the ISA, but it can + * only be accesses via a vector register. Expose VSCR as a 32-bit register + * even though the kernel represents it as a 128-bit vector. + */ #define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81) /* Virtual processor areas */ diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index 4ba75f6..fe15a94 100644 --- a/arch/powerpc/kvm/booke.c +++ b/arch/powerpc/kvm/booke.c @@ -1634,6 +1634,23 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) case KVM_REG_PPC_VRSAVE: val = get_reg_val(reg->id, vcpu->arch.vrsave); break; +#ifdef CONFIG_ALTIVEC + case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31: + if (!cpu_has_feature(CPU_FTR_ALTIVEC)) { + r = -ENXIO; + break; + } + val.vval = vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0]; + break; + case KVM_REG_PPC_VSCR: + if (!cpu_has_feature(CPU_FTR_ALTIVEC)) { + r = -ENXIO; + break; + } + val = get_reg_val(reg->id, vcpu->arch.vr.vscr.u[3]); + break; +#endif /* CONFIG_ALTIVEC */ + default: r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, reg->id, &val); break; @@ -1717,6 +1734,23 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) case KVM_REG_PPC_VRSAVE: vcpu->arch.vrsave = set_reg_val(reg->id, val); break; +#ifdef CONFIG_ALTIVEC + case KVM_REG_PPC_VR0 ... KVM_REG_PPC_VR31: + if (!cpu_has_feature(CPU_FTR_ALTIVEC)) { + r = -ENXIO; + break; + } + vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0] = val.vval; + break; + case KVM_REG_PPC_VSCR: + if (!cpu_has_feature(CPU_FTR_ALTIVEC)) { + r = -ENXIO; + break; + } + vcpu->arch.vr.vscr.u[3] = set_reg_val(reg->id, val); + break; +#endif /* CONFIG_ALTIVEC */ + default: r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, reg->id, &val); break;
Add ONE_REG support for AltiVec on Book3E. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> --- v2: - add comment describing VCSR register representation in KVM vs kernel arch/powerpc/include/uapi/asm/kvm.h | 5 +++++ arch/powerpc/kvm/booke.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+)