From patchwork Mon Jun 30 07:55:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Shawcroft X-Patchwork-Id: 365502 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5D4A81400EE for ; Mon, 30 Jun 2014 17:55:38 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=MLSDH1BNQzsUxqqwDYdpDZwO+wK61W8vJVbwXIS9Ut72Wy 5g7/w1sYfK705TFT3BkxREAurXVL//cnER/sDVoZNTm1B/uvmSWjJSw8BZYvxc95 52rDaSGWBvZ4X/Q7/PFsouMPskoJuinXGy5JpIkIywaXRPkPYAawscvXrAXv4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=GZlW45xPs+s41JXl7lOvkF0YJz8=; b=MMbwe033vtt4OohcGVB4 cEeJJ5B/lSDPQ/8gDBHZbo891uAjpmOw1PUwiVHH62wvOi8LBf0/pZGZoy47e7na a4Enj1CUF2ItdV3FhLY196tGUJxg0JLJjt3zc3iQMYzpeYRGcJxbAegSZ/cpm05L 36Nf9csZXrEbJkrW3tOkj50= Received: (qmail 21350 invoked by alias); 30 Jun 2014 07:55:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 21308 invoked by uid 89); 30 Jun 2014 07:55:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 30 Jun 2014 07:55:26 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 30 Jun 2014 08:55:24 +0100 Received: from [10.1.207.52] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 30 Jun 2014 08:55:22 +0100 Message-ID: <53B117E9.6040806@arm.com> Date: Mon, 30 Jun 2014 08:55:21 +0100 From: Marcus Shawcroft User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [Committed][AArch64] Fix register clobber in, aarch64_ashr_sisd_or_int_3 split. X-MC-Unique: 114063008552401401 Hi, Fixing PR target/61633 The two split patterns associated with aarch64_ashr_sisd_or_int_3 split the instruction into a NEG followed by an SHL. The split uses one of the input operands as a scratch register to hold the output of the NEG resulting in register corruption. This patch adjusts the splits to use the output operand as the scratch register. Regressed aarch64-none-elf. Committed to trunk as r212137. Back port to 4.9 coming shortly. /Marcus 2014-06-30 Marcus Shawcroft PR target/61633 * config/aarch64/aarch64.md (*aarch64_ashr_sisd_or_int_3): Add alternative; make early clobber. Adjust both split patterns to use operand 0 as the working register. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 8705ee9..3eb783c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3057,17 +3057,18 @@ ;; Arithmetic right shift using SISD or Integer instruction (define_insn "*aarch64_ashr_sisd_or_int_3" - [(set (match_operand:GPI 0 "register_operand" "=w,w,r") + [(set (match_operand:GPI 0 "register_operand" "=w,&w,&w,r") (ashiftrt:GPI - (match_operand:GPI 1 "register_operand" "w,w,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us,w,rUs")))] + (match_operand:GPI 1 "register_operand" "w,w,w,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us,w,0,rUs")))] "" "@ sshr\t%0, %1, %2 # + # asr\t%0, %1, %2" - [(set_attr "simd" "yes,yes,no") - (set_attr "type" "neon_shift_imm,neon_shift_reg,shift_reg")] + [(set_attr "simd" "yes,yes,yes,no") + (set_attr "type" "neon_shift_imm,neon_shift_reg,neon_shift_reg,shift_reg")] ) (define_split @@ -3076,11 +3077,13 @@ (match_operand:DI 1 "aarch64_simd_register") (match_operand:QI 2 "aarch64_simd_register")))] "TARGET_SIMD && reload_completed" - [(set (match_dup 2) + [(set (match_dup 3) (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) (set (match_dup 0) - (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SISD_SSHL))] - "" + (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_SISD_SSHL))] +{ + operands[3] = gen_lowpart (QImode, operands[0]); +} ) (define_split @@ -3089,11 +3092,13 @@ (match_operand:SI 1 "aarch64_simd_register") (match_operand:QI 2 "aarch64_simd_register")))] "TARGET_SIMD && reload_completed" - [(set (match_dup 2) + [(set (match_dup 3) (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) (set (match_dup 0) - (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_SSHL_2S))] - "" + (unspec:SI [(match_dup 1) (match_dup 3)] UNSPEC_SSHL_2S))] +{ + operands[3] = gen_lowpart (QImode, operands[0]); +} ) (define_insn "*aarch64_sisd_ushl" -- 1.7.9.5