Patchwork [v3,1/3] powerpc/fsl: 85xx: document cache-sram size as a kernel parametric option

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Submitter Vivek Mahajan
Date Oct. 21, 2009, 12:50 p.m.
Message ID <1256129459-10685-1-git-send-email-vivek.mahajan@freescale.com>
Download mbox | patch
Permalink /patch/36542/
State Superseded
Delegated to: Kumar Gala
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Comments

Vivek Mahajan - Oct. 21, 2009, 12:50 p.m.
Adds documentation for the size parameter of Freescale's QorIQ
based cache-sram

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
---
v2, v3: No change over v1

 Documentation/kernel-parameters.txt |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

Patch

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 6fa7292..8767f36 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -412,6 +412,9 @@  and is between 256 and 4096 characters. It is defined in the file
 
 	c101=		[NET] Moxa C101 synchronous serial card
 
+	cache-sram-size=	[PPC] Size of Freescale's QorIQ Cache SRAM
+			See Documentation/powerpc/fsl_85xx_cache_sram.txt.
+
 	cachesize=	[BUGS=X86-32] Override level 2 CPU cache size detection.
 			Sometimes CPU hardware bugs make them report the cache
 			size incorrectly. The kernel will attempt work arounds