| Message ID | 1403917351-13215-1-git-send-email-thierry.reding@gmail.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Sat, Jun 28, 2014 at 02:02:28AM +0100, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by > the AVP coprocessor and can also serve as a backup for the ARM Cortex > CPU's local interrupt controller (GIC). > > The LIC is subdivided into multiple identical units, each handling 32 > possible interrupt sources. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v2: > - new patch > > .../interrupt-controller/nvidia,tegra20-ictlr.txt | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt > new file mode 100644 > index 000000000000..c695ec713740 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt > @@ -0,0 +1,19 @@ > +NVIDIA Tegra Legacy Interrupt Controller > + > +The legacy interrupt controller is divided into units that serve 32 interrupts > +each. Tegra20 implements four units, whereas Tegra30 and later implement five. > + > +Required properties: > +- compatible: "nvidia,tegra<chip>-ictlr" And valid <chip> values are? > +- reg: Physical base address and length of the controller's registers. There > + should be one entry for each unit. > + > +Example: > + > + interrupt-controller@60004000 { > + compatible = "nvidia,tegra20-ictlr"; > + reg = <0x60004000 0x40 /* primary controller */ > + 0x60004100 0x40 /* secondary controller */ > + 0x60004200 0x40 /* tertiary controller */ > + 0x60004300 0x40>; /* quaternary controller */ Could we please bracket the entries individually, e.g. reg = <0x60004000 0x40>, <0x60004100 0x40>, <0x60004200 0x40>, <0x60004300 0x40>; How do the interrupt lines correspond to those of the GIC? Cheers, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 06/30/2014 11:43 AM, Mark Rutland wrote: > On Sat, Jun 28, 2014 at 02:02:28AM +0100, Thierry Reding wrote: >> From: Thierry Reding <treding@nvidia.com> >> >> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by >> the AVP coprocessor and can also serve as a backup for the ARM Cortex >> CPU's local interrupt controller (GIC). >> >> The LIC is subdivided into multiple identical units, each handling 32 >> possible interrupt sources. >> >> Signed-off-by: Thierry Reding <treding@nvidia.com> >> --- >> Changes in v2: >> - new patch >> >> .../interrupt-controller/nvidia,tegra20-ictlr.txt | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt >> new file mode 100644 >> index 000000000000..c695ec713740 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt >> @@ -0,0 +1,19 @@ >> +NVIDIA Tegra Legacy Interrupt Controller >> + >> +The legacy interrupt controller is divided into units that serve 32 interrupts >> +each. Tegra20 implements four units, whereas Tegra30 and later implement five. >> + >> +Required properties: >> +- compatible: "nvidia,tegra<chip>-ictlr" > > And valid <chip> values are? Do you really want us to edit every single binding every time a new chip comes out? Surely just relying NVIDIA's published chip names is fine? -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 06/27/2014 07:02 PM, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by > the AVP coprocessor and can also serve as a backup for the ARM Cortex > CPU's local interrupt controller (GIC). > > The LIC is subdivided into multiple identical units, each handling 32 > possible interrupt sources. The series looks OK to me, although I guess there will be a V3 to address Mark's comments? -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Jun 30, 2014 at 07:38:13PM +0100, Stephen Warren wrote: > On 06/30/2014 11:43 AM, Mark Rutland wrote: > > On Sat, Jun 28, 2014 at 02:02:28AM +0100, Thierry Reding wrote: > >> From: Thierry Reding <treding@nvidia.com> > >> > >> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by > >> the AVP coprocessor and can also serve as a backup for the ARM Cortex > >> CPU's local interrupt controller (GIC). > >> > >> The LIC is subdivided into multiple identical units, each handling 32 > >> possible interrupt sources. > >> > >> Signed-off-by: Thierry Reding <treding@nvidia.com> > >> --- > >> Changes in v2: > >> - new patch > >> > >> .../interrupt-controller/nvidia,tegra20-ictlr.txt | 19 +++++++++++++++++++ > >> 1 file changed, 19 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt > >> > >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt > >> new file mode 100644 > >> index 000000000000..c695ec713740 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt > >> @@ -0,0 +1,19 @@ > >> +NVIDIA Tegra Legacy Interrupt Controller > >> + > >> +The legacy interrupt controller is divided into units that serve 32 interrupts > >> +each. Tegra20 implements four units, whereas Tegra30 and later implement five. > >> + > >> +Required properties: > >> +- compatible: "nvidia,tegra<chip>-ictlr" > > > > And valid <chip> values are? > > Do you really want us to edit every single binding every time a new chip > comes out? Surely just relying NVIDIA's published chip names is fine? > While I am not a fan of wildcards in documentation, if you feel this is clear as is then feel free to leave it as-is. The example is probably sufficient. Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 06/30/2014 02:32 PM, Stephen Warren wrote: > On 06/27/2014 07:02 PM, Thierry Reding wrote: >> From: Thierry Reding <treding@nvidia.com> >> >> The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by >> the AVP coprocessor and can also serve as a backup for the ARM Cortex >> CPU's local interrupt controller (GIC). >> >> The LIC is subdivided into multiple identical units, each handling 32 >> possible interrupt sources. > > The series looks OK to me, although I guess there will be a V3 to > address Mark's comments? Thierry, do you still want this series applied? I'm not sure if it's required by or conflicts with any of your later patches to move code out of arch/arm/mach-tegra/? If this series should still be applied, I guess I can fix up Mark's remaining comment (the bracketing of the multiple reg entries in the DT) when applying it, at least if you don't want to repost it yourself. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Aug 25, 2014 at 11:35:42AM -0600, Stephen Warren wrote: > On 06/30/2014 02:32 PM, Stephen Warren wrote: > >On 06/27/2014 07:02 PM, Thierry Reding wrote: > >>From: Thierry Reding <treding@nvidia.com> > >> > >>The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by > >>the AVP coprocessor and can also serve as a backup for the ARM Cortex > >>CPU's local interrupt controller (GIC). > >> > >>The LIC is subdivided into multiple identical units, each handling 32 > >>possible interrupt sources. > > > >The series looks OK to me, although I guess there will be a V3 to > >address Mark's comments? > > Thierry, do you still want this series applied? I'm not sure if it's > required by or conflicts with any of your later patches to move code out of > arch/arm/mach-tegra/? > > If this series should still be applied, I guess I can fix up Mark's > remaining comment (the bracketing of the multiple reg entries in the DT) > when applying it, at least if you don't want to repost it yourself. This was originally meant to be moved out of arch/arm/mach-tegra and shared for upcoming 64-bit SoCs, but it seems like we may not need this code for 64-bit at all. On the other hand the series is an improvement over what we've had before, so there may still be some value in merging it. I'll respin v3. Thierry
diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt new file mode 100644 index 000000000000..c695ec713740 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt @@ -0,0 +1,19 @@ +NVIDIA Tegra Legacy Interrupt Controller + +The legacy interrupt controller is divided into units that serve 32 interrupts +each. Tegra20 implements four units, whereas Tegra30 and later implement five. + +Required properties: +- compatible: "nvidia,tegra<chip>-ictlr" +- reg: Physical base address and length of the controller's registers. There + should be one entry for each unit. + +Example: + + interrupt-controller@60004000 { + compatible = "nvidia,tegra20-ictlr"; + reg = <0x60004000 0x40 /* primary controller */ + 0x60004100 0x40 /* secondary controller */ + 0x60004200 0x40 /* tertiary controller */ + 0x60004300 0x40>; /* quaternary controller */ + };