From patchwork Fri Jun 27 13:25:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel Fernandez X-Patchwork-Id: 364965 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C6B571400DE for ; Fri, 27 Jun 2014 23:28:14 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753534AbaF0N0h (ORCPT ); Fri, 27 Jun 2014 09:26:37 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:34844 "EHLO mx08-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752822AbaF0N0e (ORCPT ); Fri, 27 Jun 2014 09:26:34 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id s5RDPqBL006918; Fri, 27 Jun 2014 15:25:52 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 1mrkkfpsb1-1 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NOT); Fri, 27 Jun 2014 15:25:52 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8FFCB5B; Fri, 27 Jun 2014 13:25:35 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E2C5F2D3B6; Fri, 27 Jun 2014 13:25:34 +0000 (GMT) Received: from lmenx315.lme.st.com ([10.201.19.41]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BZP07288 (AUTH frq07381); Fri, 27 Jun 2014 15:25:31 +0200 From: Gabriel FERNANDEZ To: mturquette@linaro.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, Lee Jones , Gabriel Fernandez Subject: [PATCH v2 04/14] clk: st: Adds Flexgen clock binding Date: Fri, 27 Jun 2014 15:25:01 +0200 Message-Id: <1403875511-7710-5-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1403875511-7710-1-git-send-email-gabriel.fernandez@linaro.org> References: <1403875511-7710-1-git-send-email-gabriel.fernandez@linaro.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.12.52, 1.0.14, 0.0.0000 definitions=2014-06-27_03:2014-06-27, 2014-06-27, 1970-01-01 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A Flexgen structure is composed by: - a clock cross bar (represented by a mux element) - a pre and final dividers (represented by a divider and gate elements) Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- .../devicetree/bindings/clock/st/st,clkgen.txt | 5 +++ .../devicetree/bindings/clock/st/st,flexgen.txt | 48 ++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt index 427bad8..78978f1 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt @@ -32,6 +32,10 @@ address is common of all subnode. vcc_node { ... }; + + flexgen_node { + ... + }; ... }; @@ -45,6 +49,7 @@ Each subnode should use the binding discribe in [2]..[7] [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt [6] Documentation/devicetree/bindings/clock/st,vcc.txt [7] Documentation/devicetree/bindings/clock/st,quadfs.txt +[8] Documentation/devicetree/bindings/clock/st,flexgen.txt Required properties: diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt new file mode 100644 index 0000000..f2d4333 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -0,0 +1,48 @@ +Binding for a type of flexgen structure found on certain +STMicroelectronics consumer electronics SoC devices + +This structure includes: +- a clock cross bar (represented by a mux element) +- a pre and final dividers (represented by a divider and gate elements) + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be: + "st,flexgen" + +- #clock-cells : from common clock binding; shall be set to 1. + +- clocks : from common clock binding + +- clock-output-names : From common clock binding. The block has 4 + clock outputs but not all of them in a specific instance + have to be used in the SoC. If a clock name is left as + an empty string then no clock will be created for the + output associated with that string index. If fewer than + 4 strings are provided then no clocks will be created + for the remaining outputs. + +Example: + + clockgen-d2@x9106000 { + compatible = "st,clkgen-c32"; + reg = <0x9106000 0x1000>; + + clk_s_d2_flexgen: clk-s-d2-flexgen { + compatible = "st,flexgen"; + + #clock-cells = <1>; + clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 2>, + <&clk_s_d2_quadfs 3>; + + clock-output-names = "clk-pix-main-disp", + "clk-pix-pip", + "clk-pix-gdp1", + "clk-pix-gdp2"; + }; + };