diff mbox

[v2,1/3] of: Add NVIDIA Tegra flow controller bindings

Message ID 1403870848-1754-1-git-send-email-thierry.reding@gmail.com
State Superseded, archived
Headers show

Commit Message

Thierry Reding June 27, 2014, 12:07 p.m. UTC
From: Thierry Reding <treding@nvidia.com>

Add device tree bindings for the flow controller found on NVIDIA Tegra
SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/arm/tegra/nvidia,tegra114-flowctrl.txt          | 12 ++++++++++++
 .../bindings/arm/tegra/nvidia,tegra124-flowctrl.txt          | 12 ++++++++++++
 .../bindings/arm/tegra/nvidia,tegra20-flowctrl.txt           | 12 ++++++++++++
 .../bindings/arm/tegra/nvidia,tegra30-flowctrl.txt           | 12 ++++++++++++
 4 files changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-flowctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-flowctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-flowctrl.txt

Comments

Stephen Warren June 27, 2014, 9:20 p.m. UTC | #1
On 06/27/2014 06:07 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add device tree bindings for the flow controller found on NVIDIA Tegra
> SoCs.
> 

> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt

> +NVIDIA Tegra20 Flow Controller
> +
> +Required properties:
> +- compatible: "nvidia,tegra20-flowctrl"
> +- reg: Should contain one register range (address and length)
> +
> +Example:
> +
> +	flow-controller@60007000 {
> +		compatible = "nvidia,tegra20-flowctrl";
> +		reg = <0x60007000 0x1000>;
> +	};

The bindings all have the same structure. Can we collapse them all into
this one file and just list all the valid compatible values and say pick
one?
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Stephen Warren June 27, 2014, 9:20 p.m. UTC | #2
On 06/27/2014 06:07 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> These nodes are required so that the flow controller driver can obtain
> the I/O memory region from device tree rather than hard-coding it.

This patch,
Acked-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren June 27, 2014, 9:21 p.m. UTC | #3
On 06/27/2014 06:07 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Use a matching device tree node to initialize the flow controller driver
> instead of hard-coding the I/O address. This is necessary to get rid of
> the iomap.h include, which in turn make it easier to share this code
> with 64-bit Tegra SoCs.

This patch,
Acked-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren Aug. 25, 2014, 5:32 p.m. UTC | #4
On 06/27/2014 03:20 PM, Stephen Warren wrote:
> On 06/27/2014 06:07 AM, Thierry Reding wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> Add device tree bindings for the flow controller found on NVIDIA Tegra
>> SoCs.
>>
>
>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
>
>> +NVIDIA Tegra20 Flow Controller
>> +
>> +Required properties:
>> +- compatible: "nvidia,tegra20-flowctrl"
>> +- reg: Should contain one register range (address and length)
>> +
>> +Example:
>> +
>> +	flow-controller@60007000 {
>> +		compatible = "nvidia,tegra20-flowctrl";
>> +		reg = <0x60007000 0x1000>;
>> +	};
>
> The bindings all have the same structure. Can we collapse them all into
> this one file and just list all the valid compatible values and say pick
> one?

Thierry, did you post an updated version of this patch? If so, I seem to 
have lost it, so a repost would be good. Thanks.
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Thierry Reding Aug. 26, 2014, 6 a.m. UTC | #5
On Mon, Aug 25, 2014 at 11:32:20AM -0600, Stephen Warren wrote:
> On 06/27/2014 03:20 PM, Stephen Warren wrote:
> >On 06/27/2014 06:07 AM, Thierry Reding wrote:
> >>From: Thierry Reding <treding@nvidia.com>
> >>
> >>Add device tree bindings for the flow controller found on NVIDIA Tegra
> >>SoCs.
> >>
> >
> >>diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
> >
> >>+NVIDIA Tegra20 Flow Controller
> >>+
> >>+Required properties:
> >>+- compatible: "nvidia,tegra20-flowctrl"
> >>+- reg: Should contain one register range (address and length)
> >>+
> >>+Example:
> >>+
> >>+	flow-controller@60007000 {
> >>+		compatible = "nvidia,tegra20-flowctrl";
> >>+		reg = <0x60007000 0x1000>;
> >>+	};
> >
> >The bindings all have the same structure. Can we collapse them all into
> >this one file and just list all the valid compatible values and say pick
> >one?
> 
> Thierry, did you post an updated version of this patch? If so, I seem to
> have lost it, so a repost would be good. Thanks.

I don't think I did. If my memory serves me well then I did address your
comments but never sent out the patches. I'll check what the status is.

Thierry
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-flowctrl.txt
new file mode 100644
index 000000000000..72599fdb09a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra114-flowctrl.txt
@@ -0,0 +1,12 @@ 
+NVIDIA Tegra114 Flow Controller
+
+Required properties:
+- compatible: "nvidia,tegra114-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra114-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-flowctrl.txt
new file mode 100644
index 000000000000..3af5fe2019f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-flowctrl.txt
@@ -0,0 +1,12 @@ 
+NVIDIA Tegra124 Flow Controller
+
+Required properties:
+- compatible: "nvidia,tegra124-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+	flow-controller@0,60007000 {
+		compatible = "nvidia,tegra124-flowctrl";
+		reg = <0x0 0x60007000 0x0 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
new file mode 100644
index 000000000000..b077ca8a22c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
@@ -0,0 +1,12 @@ 
+NVIDIA Tegra20 Flow Controller
+
+Required properties:
+- compatible: "nvidia,tegra20-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra20-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-flowctrl.txt
new file mode 100644
index 000000000000..72c90dd59110
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-flowctrl.txt
@@ -0,0 +1,12 @@ 
+NVIDIA Tegra30 Flow Controller
+
+Required properties:
+- compatible: "nvidia,tegra30-flowctrl"
+- reg: Should contain one register range (address and length)
+
+Example:
+
+	flow-controller@60007000 {
+		compatible = "nvidia,tegra30-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};