[U-Boot] driver/ddr: Fix DDR register timing_cfg_8

Submitted by York Sun on June 26, 2014, 6:14 p.m.

Details

Message ID 1403806484-13190-1-git-send-email-yorksun@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

York Sun June 26, 2014, 6:14 p.m.
The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 drivers/ddr/fsl/ctrl_regs.c |    3 +++
 1 file changed, 3 insertions(+)

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diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index dcf6287..04e4178 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1857,6 +1857,9 @@  static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
 
 	acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
 	wrtord_bg = max(4, picos_to_mclk(7500));
+	if (popts->otf_burst_chop_en)
+		wrtord_bg += 2;
+
 	pre_all_rec = 0;
 
 	ddr->timing_cfg_8 = (0