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Thu, 26 Jun 2014 17:03:35 +0900 (KST) X-AuditID: cbfee690-b7fb56d000003439-c6-53abd3d7a89c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 38.86.05196.7D3DBA35; Thu, 26 Jun 2014 17:03:35 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N7R00LRHNPHRI40@mmp1.samsung.com>; Thu, 26 Jun 2014 17:03:34 +0900 (KST) From: Ajay Kumar To: u-boot@lists.denx.de Date: Thu, 26 Jun 2014 13:31:00 +0530 Message-id: <1403769668-2026-3-git-send-email-ajaykumar.rs@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1403769668-2026-1-git-send-email-ajaykumar.rs@samsung.com> References: <1403769668-2026-1-git-send-email-ajaykumar.rs@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrILMWRmVeSWpSXmKPExsWyRsSkSvf65dXBBh/W8VsceH+QxWLDm4XM FtfP21l0HGlhtFh1eAO7xbct2xgt3u7tZHdg95jdcJHFY+esu+weZ+/sYPTo27KKMYAlissm JTUnsyy1SN8ugSvjZk8zW8FnwYotizqZGhhn8XcxcnJICJhIXFm+hQnCFpO4cG89WxcjF4eQ wFJGiQ3nHzDDFPVOXcgKkVjEKPFx8S0mCGcCk8Si14sZQarYBLQltk2/yQJiiwhISPzqv8oI UsQsMINR4uiDaWA7hAXsJF7/6AEq4uBgEVCVWDaHDSTMK+AusffvTDaQsISAgsScSTYgYU4B D4npf1+DjRQCKvl77jTYdRIC09klVjeeYwVJsAgISHybfIgFoldWYtMBqKMlJQ6uuMEygVF4 ASPDKkbR1ILkguKk9CITveLE3OLSvHS95PzcTYzA4D7979mEHYz3DlgfYkwGGjeRWUo0OR8Y HXkl8YbGZkYWpiamxkbmlmakCSuJ86o9SgoSEkhPLEnNTk0tSC2KLyrNSS0+xMjEwSnVwBgi IKX/5rqPhhRfK/vpcws/sRbX7HncsD2ANa4lt/FK65/fP9tzRLhDZhnd+fZnEp9D5Kq/VnGT VOdu8ziYde1o++qZTg+D1hQcf/deTePgq/SqgCcL7j64kR5ndrs7pj5j4svi3+m214SFeZN7 OFfY/qzz/na+etZ64bKk8xmx4ndd5jWzcyuxFGckGmoxFxUnAgCwNOA/hAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsVy+t9jAd3rl1cHG8xbw25x4P1BFosNbxYy W1w/b2fRcaSF0WLV4Q3sFt+2bGO0eLu3k92B3WN2w0UWj52z7rJ7nL2zg9Gjb8sqxgCWqAZG m4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygE5QUyhJz SoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGTd7mtkKPgtWbFnUydTAOIu/i5GT Q0LARKJ36kJWCFtM4sK99WxdjFwcQgKLGCU+Lr7FBOFMYJJY9HoxI0gVm4C2xLbpN1lAbBEB CYlf/VcZQYqYBWYwShx9MI0JJCEsYCfx+kcPUBEHB4uAqsSyOWwgYV4Bd4m9f2eygYQlBBQk 5kyyAQlzCnhITP/7GmykEFDJ33On2SYw8i5gZFjFKJpakFxQnJSea6RXnJhbXJqXrpecn7uJ ERw7z6R3MK5qsDjEKMDBqMTD++HxqmAh1sSy4srcQ4wSHMxKIrzv/wKFeFMSK6tSi/Lji0pz UosPMZoC3TSRWUo0OR8Y13kl8YbGJuamxqaWJhYmZpZK4rwHW60DhQTSE0tSs1NTC1KLYPqY ODilGhhtv11W+fVj+szZzKteh39se3DAwV7wZtauWUlXf2dOiYz+8IjPR+6NV2mvhrzXz4TQ a6Zf8y8a3JTVm9tzgn+SemnWFcu+BRHTft7r3Cgbn/VAMLaf1cLmT2dN0oQLt3a6zz0ddLzg Z+U6j6VaHjILrua9b2I6xlW9U/bF3DeX/FPWsuoF7ClQYinOSDTUYi4qTgQATRaLy7MCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: dh09.lee@samsung.com, prashanth.g@samsung.com, Ajay Kumar Subject: [U-Boot] [PATCH V2 02/10] arm: exynos: Add RPLL for Exynos5420 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de RPLL is needed to drive the LCD panel on Exynos5420 based boards. Signed-off-by: Ajay Kumar Acked-by: Simon Glass Tested-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock_init.h | 3 +++ arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index a875d0b..fce502f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -75,6 +75,9 @@ struct mem_timings { unsigned spll_mdiv; unsigned spll_pdiv; unsigned spll_sdiv; + unsigned rpll_mdiv; + unsigned rpll_pdiv; + unsigned rpll_sdiv; unsigned pclk_cdrex_ratio; unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index 1d6977f..b6a9bc1 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, + /* RPLL @70.5Mhz */ + .rpll_mdiv = 0x5E, + .rpll_pdiv = 0x2, + .rpll_sdiv = 0x4, .direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70, @@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void) writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock); writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock); writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock); + writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock); setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK); @@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void) while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) ; + /* Set RPLL */ + writel(RPLL_CON2_VAL, &clk->rpll_con2); + writel(RPLL_CON1_VAL, &clk->rpll_con1); + val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv); + writel(val, &clk->rpll_con0); + while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0) + ; + writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);