@@ -196,6 +196,11 @@ static u32 get_i2c_clk(void)
return get_ipg_clk();
}
+static u32 get_dspi_clk(void)
+{
+ return get_ipg_clk();
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
@@ -213,6 +218,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_fec_clk();
case MXC_I2C_CLK:
return get_i2c_clk();
+ case MXC_DSPI_CLK:
+ return get_dspi_clk();
default:
break;
}
@@ -17,6 +17,7 @@ enum mxc_clock {
MXC_ESDHC_CLK,
MXC_FEC_CLK,
MXC_I2C_CLK,
+ MXC_DSPI_CLK,
};
void enable_ocotp_clk(unsigned char enable);
@@ -176,6 +176,7 @@ struct anadig_reg {
#define CCM_REG_CTRL_MASK 0xffffffff
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
@@ -22,6 +22,10 @@
#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE | PAD_CTL_DSE_25ohm | \
+ PAD_CTL_SPEED_MED)
+#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE | PAD_CTL_DSE_25ohm | \
+ PAD_CTL_SPEED_MED)
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
@@ -56,6 +60,10 @@ enum {
VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+ VF610_PAD_PTB19__DSPI0_CS0 = IOMUX_PAD(0x00a4, 0x00a4, 1, __NA_, 0, VF610_DSPI_PAD_CTRL),
+ VF610_PAD_PTB20__DSPI0_SIN = IOMUX_PAD(0x00a8, 0x00a8, 1, __NA_, 0, VF610_DSPI_SIN_PAD_CTRL),
+ VF610_PAD_PTB21__DSPI0_SOUT = IOMUX_PAD(0x00ac, 0x00ac, 1, __NA_, 0, VF610_DSPI_PAD_CTRL),
+ VF610_PAD_PTB22__DSPI0_SCK = IOMUX_PAD(0x00b0, 0x00b0, 1, __NA_, 0, VF610_DSPI_PAD_CTRL),
VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
@@ -133,6 +133,8 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PKE (1 << 3)
#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
+#define PAD_CTL_OBE (1 << 1)
+#define PAD_CTL_IBE (1 << 0)
#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)