| Message ID | 1403177830-28595-1-git-send-email-thierry.reding@gmail.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
On 06/19/2014 05:37 AM, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads > that lanes can be assigned to in order to support a variety of interface > options: USB 2.0, USB 3.0, PCIe and SATA. > > In addition to the pin controller used to assign lanes to pads two PHYs > are exposed to allow the bricks for PCIe and SATA to be powered up and > down by PCIe and SATA drivers. Linus, does the driver look OK? I'm hoping for an ack from you so that I can take this series through the Tegra tree to resolve some dependencies; we have various other drivers that depend on this series. Thanks! -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Jun 30, 2014 at 6:04 PM, Stephen Warren <swarren@wwwdotorg.org> wrote: > On 06/19/2014 05:37 AM, Thierry Reding wrote: >> From: Thierry Reding <treding@nvidia.com> >> >> The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads >> that lanes can be assigned to in order to support a variety of interface >> options: USB 2.0, USB 3.0, PCIe and SATA. >> >> In addition to the pin controller used to assign lanes to pads two PHYs >> are exposed to allow the bricks for PCIe and SATA to be powered up and >> down by PCIe and SATA drivers. > > Linus, does the driver look OK? I'm hoping for an ack from you so that I > can take this series through the Tegra tree to resolve some > dependencies; we have various other drivers that depend on this series. Sure thing, if it looks OK to you, by all means apply it yo your tree. Acked-by: Linus Walleij <linus.walleij@linaro.org> (Also goes for the DT bindings FWIW) Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Jun 19, 2014 at 01:37:07PM +0200, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > This patch adds the device tree binding documentation for the XUSB pad > controller found on NVIDIA Tegra SoCs. It exposes both pinmuxing and PHY > capabilities. > > Tested-by: Mikko Perttunen <mperttunen@nvidia.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v4: > - drop unneeded #address-cells = <0> and #size-cells = <0> > > Changes in v2: > - move header file to this patch and refer to it in the binding > - update example to match the latest binding > > .../pinctrl/nvidia,tegra124-xusb-padctl.txt | 127 +++++++++++++++++++++ > include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 ++ > 2 files changed, 134 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt > create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h Patches 1 and 2 applied to the for-3.17/xusb-padctl branch with Linus' Acked-by. Thierry
On Thu, Jun 19, 2014 at 01:37:09PM +0200, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The device tree node in the SoC file contains only the resources (such > as registers, resets, ...) but none of the lane assignment information > since that's board specific and belongs in the board file. > > Tested-by: Mikko Perttunen <mperttunen@nvidia.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v2: > - include dt-bindings/pinctrl/pinctrl-tegra-xusb.h so that board files > don't have to include it explicitly > - remove unneeded #address-cells/#size-cells = <0> > - add padctl label for XUSB pad controller node > > arch/arm/boot/dts/tegra124.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) Patches 3 and 4 applied to the for-3.17/dt branch and rebased the branch on for-3.17/xusb-padctl because of the dependency on the dt-bindings header. Thierry
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt new file mode 100644 index 000000000000..2f9c0bd66457 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt @@ -0,0 +1,127 @@ +Device tree binding for NVIDIA Tegra XUSB pad controller +======================================================== + +The Tegra XUSB pad controller manages a set of lanes, each of which can be +assigned to one out of a set of different pads. Some of these pads have an +associated PHY that must be powered up before the pad can be used. + +This document defines the device-specific binding for the XUSB pad controller. + +Refer to pinctrl-bindings.txt in this directory for generic information about +pin controller device tree bindings and ../phy/phy-bindings.txt for details on +how to describe and reference PHYs in device trees. + +Required properties: +-------------------- +- compatible: should be "nvidia,tegra124-xusb-padctl" +- reg: Physical base address and length of the controller's registers. +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - padctl +- #phy-cells: Should be 1. The specifier is the index of the PHY to reference. + See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values. + +Lane muxing: +------------ + +Child nodes contain the pinmux configurations following the conventions from +the pinctrl-bindings.txt document. Typically a single, static configuration is +given and applied at boot time. + +Each subnode describes groups of lanes along with parameters and pads that +they should be assigned to. The name of these subnodes is not important. All +subnodes should be parsed solely based on their content. + +Each subnode only applies the parameters that are explicitly listed. In other +words, if a subnode that lists a function but no pin configuration parameters +implies no information about any pin configuration parameters. Similarly, a +subnode that describes only an IDDQ parameter implies no information about +what function the pins are assigned to. For this reason even seemingly boolean +values are actually tristates in this binding: unspecified, off or on. +Unspecified is represented as an absent property, and off/on are represented +as integer values 0 and 1. + +Required properties: +- nvidia,lanes: An array of strings. Each string is the name of a lane. + +Optional properties: +- nvidia,function: A string that is the name of the function (pad) that the + pin or group should be assigned to. Valid values for function names are + listed below. +- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes) + +Note that not all of these properties are valid for all lanes. Lanes can be +divided into three groups: + + - otg-0, otg-1, otg-2: + + Valid functions for this group are: "snps", "xusb", "uart", "rsvd". + + The nvidia,iddq property does not apply to this group. + + - ulpi-0, hsic-0, hsic-1: + + Valid functions for this group are: "snps", "xusb". + + The nvidia,iddq property does not apply to this group. + + - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0: + + Valid functions for this group are: "pcie", "usb3", "sata", "rsvd". + + +Example: +======== + +SoC file extract: +----------------- + + padctl@0,7009f000 { + compatible = "nvidia,tegra124-xusb-padctl"; + reg = <0x0 0x7009f000 0x0 0x1000>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + #phy-cells = <1>; + }; + +Board file extract: +------------------- + + pcie-controller@0,01003000 { + ... + + phys = <&padctl 0>; + phy-names = "pcie"; + + ... + }; + + ... + + padctl: padctl@0,7009f000 { + pinctrl-0 = <&padctl_default>; + pinctrl-names = "default"; + + padctl_default: pinmux { + usb3 { + nvidia,lanes = "pcie-0", "pcie-1"; + nvidia,function = "usb3"; + nvidia,iddq = <0>; + }; + + pcie { + nvidia,lanes = "pcie-2", "pcie-3", + "pcie-4"; + nvidia,function = "pcie"; + nvidia,iddq = <0>; + }; + + sata { + nvidia,lanes = "sata-0"; + nvidia,function = "sata"; + nvidia,iddq = <0>; + }; + }; + }; diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h new file mode 100644 index 000000000000..914d56da9324 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h @@ -0,0 +1,7 @@ +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H +#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 + +#define TEGRA_XUSB_PADCTL_PCIE 0 +#define TEGRA_XUSB_PADCTL_SATA 1 + +#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */