From patchwork Thu Oct 9 17:09:18 2008 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Steven A. Falco" X-Patchwork-Id: 3617 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 5C1E4DE924 for ; Fri, 10 Oct 2008 04:09:39 +1100 (EST) X-Original-To: linuxppc-dev@ozlabs.org Delivered-To: linuxppc-dev@ozlabs.org Received: from mlbe2k1.cs.myharris.net (mlbe2k1.cs.myharris.net [137.237.90.88]) by ozlabs.org (Postfix) with ESMTP id E8A5ADE064 for ; Fri, 10 Oct 2008 04:09:21 +1100 (EST) Received: from mail pickup service by mlbe2k1.cs.myharris.net with Microsoft SMTPSVC; Thu, 9 Oct 2008 13:09:20 -0400 Received: from saf.cs.myharris.net ([137.237.94.251]) by mlbe2k1.cs.myharris.net with Microsoft SMTPSVC(6.0.3790.1830); Thu, 9 Oct 2008 13:09:19 -0400 Message-ID: <48EE3ABE.6090007@harris.com> Date: Thu, 09 Oct 2008 13:09:18 -0400 From: "Steven A. Falco" User-Agent: Thunderbird 2.0.0.9 (X11/20071031) MIME-Version: 1.0 To: avorontsov@ru.mvista.com Subject: Re: PPC440EPx gpio driver References: <48ED1E96.4060406@harris.com> <48EE1EE1.1050206@harris.com> <20081009160803.GA20923@oksana.dev.rtsoft.ru> In-Reply-To: <20081009160803.GA20923@oksana.dev.rtsoft.ru> X-OriginalArrivalTime: 09 Oct 2008 17:09:19.0238 (UTC) FILETIME=[C4541A60:01C92A31] Cc: "linuxppc-dev@ozlabs.org" X-BeenThere: linuxppc-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Please disregard the previous version, and consider this one instead. The only difference is making better use of to_ppc4xx_gpiochip(), which helps readability. Signed-off-by: Steve Falco Reviewed-by: Anton Vorontsov diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index 033039a..589ff5c 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -13,6 +13,30 @@ #ifndef __ASM_POWERPC_PPC4xx_H__ #define __ASM_POWERPC_PPC4xx_H__ +#include + +/* GPIO */ +struct ppc4xx_gpio { + __be32 gpio_or; + __be32 gpio_tcr; + __be32 gpio_osrl; + __be32 gpio_osrh; + __be32 gpio_tsrl; + __be32 gpio_tsrh; + __be32 gpio_odr; + __be32 gpio_ir; + __be32 gpio_rr1; + __be32 gpio_rr2; + __be32 gpio_rr3; + __be32 reserved1; + __be32 gpio_isr1l; + __be32 gpio_isr1h; + __be32 gpio_isr2l; + __be32 gpio_isr2h; + __be32 gpio_isr3l; + __be32 gpio_isr3h; +}; + extern void ppc4xx_reset_system(char *cmd); #endif /* __ASM_POWERPC_PPC4xx_H__ */ diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig index 72fb35b..f4a8edb 100644 --- a/arch/powerpc/sysdev/Kconfig +++ b/arch/powerpc/sysdev/Kconfig @@ -6,3 +6,11 @@ config PPC4xx_PCI_EXPRESS bool depends on PCI && 4xx default n + +config PPC4xx_GPIO + bool "PPC4xx GPIO support" + depends on 4xx + select ARCH_REQUIRE_GPIOLIB + select GENERIC_GPIO + help + Enable gpiolib support for PPC4xx based boards diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile index a90054b..35d5765 100644 --- a/arch/powerpc/sysdev/Makefile +++ b/arch/powerpc/sysdev/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_OF_RTC) += of_rtc.o ifeq ($(CONFIG_PCI),y) obj-$(CONFIG_4xx) += ppc4xx_pci.o endif +obj-$(CONFIG_PPC4xx_GPIO) += ppc4xx_gpio.o # Temporary hack until we have migrated to asm-powerpc ifeq ($(ARCH),powerpc) diff --git a/arch/powerpc/sysdev/ppc4xx_gpio.c b/arch/powerpc/sysdev/ppc4xx_gpio.c new file mode 100644 index 0000000..93acd3f --- /dev/null +++ b/arch/powerpc/sysdev/ppc4xx_gpio.c @@ -0,0 +1,238 @@ +/* + * PPC4xx gpio driver + * + * Copyright (c) 2008 Harris Corporation + * Copyright (c) 2008 Sascha Hauer , Pengutronix + * Copyright (c) MontaVista Software, Inc. 2008. + * + * Author: Steve Falco + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +struct ppc4xx_gpio_chip { + struct of_mm_gpio_chip mm_gc; + spinlock_t lock; + u32 shadow_or; + u32 shadow_tcr; + u32 shadow_osrl; + u32 shadow_osrh; + u32 shadow_tsrl; + u32 shadow_tsrh; + u32 shadow_odr; +}; + +/* + * GPIO LIB API implementation for GPIOs + * + * There are a maximum of 64 gpios, spread over two sets of control registers. + * The sets are called GPIO0 and GPIO1. Each set is managed separately, so + * there will be two entried in the .dts file. + */ + +static inline struct ppc4xx_gpio_chip * +to_ppc4xx_gpiochip(struct of_mm_gpio_chip *mm_gc) +{ + return container_of(mm_gc, struct ppc4xx_gpio_chip, mm_gc); +} + +static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct ppc4xx_gpio __iomem *regs = mm_gc->regs; + u32 ret; + + ret = (in_be32(®s->gpio_ir) >> (31 - gpio)) & 1; + + return ret; +} + +static inline void +__ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc); + struct ppc4xx_gpio __iomem *regs = mm_gc->regs; + + if (val) + chip->shadow_or |= 1 << (31 - gpio); + else + chip->shadow_or &= ~(1 << (31 - gpio)); + out_be32(®s->gpio_or, chip->shadow_or); +} + +static void +ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc); + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + + __ppc4xx_gpio_set(gc, gpio, val); + + spin_unlock_irqrestore(&chip->lock, flags); + + pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); +} + +static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc); + struct ppc4xx_gpio __iomem *regs = mm_gc->regs; + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + + /* Disable open-drain function */ + chip->shadow_odr &= ~(1 << (31 - gpio)); + out_be32(®s->gpio_odr, chip->shadow_odr); + + /* Float the pin */ + chip->shadow_tcr &= ~(1 << (31 - gpio)); + out_be32(®s->gpio_tcr, chip->shadow_tcr); + + /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */ + if (gpio < 16) { + chip->shadow_osrl &= ~(3 << ((15 - gpio) * 2)); + out_be32(®s->gpio_osrl, chip->shadow_osrl); + + chip->shadow_tsrl &= ~(3 << ((15 - gpio) * 2)); + out_be32(®s->gpio_tsrl, chip->shadow_tsrl); + } else { + chip->shadow_osrh &= ~(3 << ((31 - gpio) * 2)); + out_be32(®s->gpio_osrh, chip->shadow_osrh); + + chip->shadow_tsrh &= ~(3 << ((31 - gpio) * 2)); + out_be32(®s->gpio_tsrh, chip->shadow_tsrh); + } + + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int +ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc); + struct ppc4xx_gpio __iomem *regs = mm_gc->regs; + unsigned long flags; + + spin_lock_irqsave(&chip->lock, flags); + + /* First set initial value */ + __ppc4xx_gpio_set(gc, gpio, val); + + /* Disable open-drain function */ + chip->shadow_odr &= ~(1 << (31 - gpio)); + out_be32(®s->gpio_odr, chip->shadow_odr); + + /* Drive the pin */ + chip->shadow_tcr |= (1 << (31 - gpio)); + out_be32(®s->gpio_tcr, chip->shadow_tcr); + + /* Bits 0-15 use TSRL, bits 16-31 use TSRH */ + if (gpio < 16) { + chip->shadow_osrl &= ~(3 << ((15 - gpio) * 2)); + out_be32(®s->gpio_osrl, chip->shadow_osrl); + + chip->shadow_tsrl &= ~(3 << ((15 - gpio) * 2)); + out_be32(®s->gpio_tsrl, chip->shadow_tsrl); + } else { + chip->shadow_osrh &= ~(3 << ((31 - gpio) * 2)); + out_be32(®s->gpio_osrh, chip->shadow_osrh); + + chip->shadow_tsrh &= ~(3 << ((31 - gpio) * 2)); + out_be32(®s->gpio_tsrh, chip->shadow_tsrh); + } + + spin_unlock_irqrestore(&chip->lock, flags); + + pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); + + return 0; +} + +static void __init ppc4xx_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) +{ + struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc); + struct ppc4xx_gpio __iomem *regs = mm_gc->regs; + + chip->shadow_or = in_be32(®s->gpio_or); + chip->shadow_tcr = in_be32(®s->gpio_tcr); + chip->shadow_osrl = in_be32(®s->gpio_osrl); + chip->shadow_osrh = in_be32(®s->gpio_osrh); + chip->shadow_tsrl = in_be32(®s->gpio_tsrl); + chip->shadow_tsrh = in_be32(®s->gpio_tsrh); + chip->shadow_odr = in_be32(®s->gpio_odr); +} + +static int __init ppc4xx_add_gpiochips(void) +{ + struct device_node *np; + + for_each_compatible_node(np, NULL, "amcc,ppc4xx-gpio") { + int ret; + struct ppc4xx_gpio_chip *ppc4xx_gc; + struct of_mm_gpio_chip *mm_gc; + struct of_gpio_chip *of_gc; + struct gpio_chip *gc; + + ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL); + if (!ppc4xx_gc) { + ret = -ENOMEM; + goto err; + } + + spin_lock_init(&ppc4xx_gc->lock); + + mm_gc = &ppc4xx_gc->mm_gc; + of_gc = &mm_gc->of_gc; + gc = &of_gc->gc; + + mm_gc->save_regs = ppc4xx_gpio_save_regs; + of_gc->gpio_cells = 2; + gc->ngpio = 32; + gc->direction_input = ppc4xx_gpio_dir_in; + gc->direction_output = ppc4xx_gpio_dir_out; + gc->get = ppc4xx_gpio_get; + gc->set = ppc4xx_gpio_set; + + ret = of_mm_gpiochip_add(np, mm_gc); + if (ret) + goto err; + continue; +err: + pr_err("%s: registration failed with status %d\n", + np->full_name, ret); + kfree(ppc4xx_gc); + /* try others anyway */ + } + return 0; +} +arch_initcall(ppc4xx_add_gpiochips);