From patchwork Thu Oct 15 05:11:57 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Neuling X-Patchwork-Id: 36047 X-Patchwork-Delegate: benh@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 03B0FB7DE4 for ; Thu, 15 Oct 2009 16:12:06 +1100 (EST) Received: by ozlabs.org (Postfix) id D4C8BB7B74; Thu, 15 Oct 2009 16:11:58 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from localhost.localdomain (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id B08CBB7B68; Thu, 15 Oct 2009 16:11:58 +1100 (EST) Received: by localhost.localdomain (Postfix, from userid 1000) id 88C3A1EA08D; Thu, 15 Oct 2009 16:11:57 +1100 (EST) Received: from neuling.org (localhost [127.0.0.1]) by localhost.localdomain (Postfix) with ESMTP id 7ED831EA08C; Thu, 15 Oct 2009 16:11:57 +1100 (EST) From: Michael Neuling To: benh@kernel.crashing.org X-GPG-Fingerprint: 9B25 DC2A C58D 2C8D 47C2 457E 0887 E86F 32E6 BE16 MIME-Version: 1.0 Subject: [PATCH] powerpc perf events: Fix priority of MSR HV vs PR bits X-Mailer: MH-E 8.0.3; nmh 1.2; GNU Emacs 22.2.1 Date: Thu, 15 Oct 2009 16:11:57 +1100 Message-ID: <15714.1255583517@neuling.org> Cc: linuxppc-dev@ozlabs.org, Paul Mackerras X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org The architecture defines that if MSR PR is set we are in problem state irrespective of the HV bit. This fixes perf events to reflect this. Signed-off-by: Michael Neuling CC: paulus@samba.org --- Tested on PHYP and BML. This could go back into 31 too with s/event/counters/g. It only effects bare metal on server chips, so no biggy if it doesn't. arch/powerpc/kernel/perf_event.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) Index: linux-2.6-ozlabs/arch/powerpc/kernel/perf_event.c =================================================================== --- linux-2.6-ozlabs.orig/arch/powerpc/kernel/perf_event.c +++ linux-2.6-ozlabs/arch/powerpc/kernel/perf_event.c @@ -116,20 +116,23 @@ static inline void perf_get_data_addr(st static inline u32 perf_get_misc_flags(struct pt_regs *regs) { unsigned long mmcra = regs->dsisr; + unsigned long sihv = MMCRA_SIHV; + unsigned long sipr = MMCRA_SIPR; if (TRAP(regs) != 0xf00) return 0; /* not a PMU interrupt */ if (ppmu->flags & PPMU_ALT_SIPR) { - if (mmcra & POWER6_MMCRA_SIHV) - return PERF_RECORD_MISC_HYPERVISOR; - return (mmcra & POWER6_MMCRA_SIPR) ? - PERF_RECORD_MISC_USER : PERF_RECORD_MISC_KERNEL; + sihv = POWER6_MMCRA_SIHV; + sipr = POWER6_MMCRA_SIPR; } - if (mmcra & MMCRA_SIHV) + + /* PR has priority over HV, so order below is important */ + if (mmcra & sipr) + return PERF_RECORD_MISC_USER; + if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV)) return PERF_RECORD_MISC_HYPERVISOR; - return (mmcra & MMCRA_SIPR) ? PERF_RECORD_MISC_USER : - PERF_RECORD_MISC_KERNEL; + return PERF_RECORD_MISC_KERNEL; } /*