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[RFC,v2,2/2] zynq: Update Zynq to init the CPU in the a9mpcore device

Message ID 622632d97d08b9609a5d2125b5686454fa939a8f.1402978426.git.alistair.francis@xilinx.com
State New
Headers show

Commit Message

Alistair Francis June 17, 2014, 4:18 a.m. UTC 
This patch removes the initialisation of the ARM Cortex-A9
in Zynq and instead allows the a9mpcore device to init the
CPU. This also updates components that rely on the CPU
and GIC, as they are now initialised in a slightly different
way

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2: - Small changes based on comments from Peter Crosthwaite
    - Updates to be compatible with the new MPCore implementation
V1: Initial Release

 hw/arm/xilinx_zynq.c |   47 ++++++++++++++++-------------------------------
 1 files changed, 16 insertions(+), 31 deletions(-)
diff mbox

Patch

diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index ba5aa82..f5de2d8 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -26,6 +26,7 @@ 
 #include "hw/loader.h"
 #include "hw/ssi.h"
 #include "qemu/error-report.h"
+#include "hw/cpu/a9mpcore.h"
 
 #define NUM_SPI_FLASHES 4
 #define NUM_QSPI_FLASHES 2
@@ -104,12 +105,10 @@  static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
 static void zynq_init(MachineState *machine)
 {
     ram_addr_t ram_size = machine->ram_size;
-    const char *cpu_model = machine->cpu_model;
     const char *kernel_filename = machine->kernel_filename;
     const char *kernel_cmdline = machine->kernel_cmdline;
     const char *initrd_filename = machine->initrd_filename;
-    ObjectClass *cpu_oc;
-    ARMCPU *cpu;
+    A9MPPrivState *mpcore;
     MemoryRegion *address_space_mem = get_system_memory();
     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
@@ -119,27 +118,8 @@  static void zynq_init(MachineState *machine)
     Error *err = NULL;
     int n;
 
-    if (!cpu_model) {
-        cpu_model = "cortex-a9";
-    }
-    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
-
-    cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
-
-    object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", &err);
-    if (err) {
-        error_report("%s", error_get_pretty(err));
-        exit(1);
-    }
-
-    object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err);
-    if (err) {
-        error_report("%s", error_get_pretty(err));
-        exit(1);
-    }
-    object_property_set_bool(OBJECT(cpu), true, "realized", &err);
-    if (err) {
-        error_report("%s", error_get_pretty(err));
+    if (machine->cpu_model) {
+        error_report("Zynq does not support CPU model override!\n");
         exit(1);
     }
 
@@ -171,16 +151,21 @@  static void zynq_init(MachineState *machine)
     qdev_init_nofail(dev);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
 
-    dev = qdev_create(NULL, "a9mpcore_priv");
-    qdev_prop_set_uint32(dev, "num-cpu", 1);
-    qdev_init_nofail(dev);
-    busdev = SYS_BUS_DEVICE(dev);
+    mpcore = A9MPCORE_PRIV(object_new("a9mpcore_priv"));
+    qdev_prop_set_uint32(DEVICE(mpcore), "num-cpu", 1);
+    qdev_prop_set_uint32(DEVICE(mpcore), "midr", ZYNQ_BOARD_MIDR);
+    qdev_prop_set_uint64(DEVICE(mpcore), "reset-cbar", MPCORE_PERIPHBASE);
+    object_property_set_bool(OBJECT(mpcore), true, "realized", &err);
+    if (err != NULL) {
+        error_report("Couldn't realize the Zynq A9MPCore: %s",
+                     error_get_pretty(err));
+        exit(1);
+    }
+    busdev = SYS_BUS_DEVICE(DEVICE(mpcore));
     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
-    sysbus_connect_irq(busdev, 0,
-                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
 
     for (n = 0; n < 64; n++) {
-        pic[n] = qdev_get_gpio_in(dev, n);
+        pic[n] = qdev_get_gpio_in(DEVICE(mpcore), n);
     }
 
     zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);