[COMMITTED,AArch64] Fix layout of frame related functions.
diff mbox

Message ID 539707F0.70302@arm.com
State New
Headers show

Commit Message

Marcus Shawcroft June 10, 2014, 1:28 p.m. UTC
Fixing various white space issues in the frame layout code.  Committed.

/Marcus

Patch
diff mbox

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index e7f455b..3eb18e9 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1917,7 +1917,6 @@  aarch64_save_or_restore_fprs (int start_offset, int increment,
   rtx (*gen_mem_ref)(enum machine_mode, rtx)
     = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM;
 
-
   for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
     {
       if (aarch64_register_saved_on_entry (regno))
@@ -1935,10 +1934,12 @@  aarch64_save_or_restore_fprs (int start_offset, int increment,
 	    {
 	      /* Empty loop.  */
 	    }
+
 	  if (regno2 <= V31_REGNUM &&
 	      aarch64_register_saved_on_entry (regno2))
 	    {
 	      rtx mem2;
+
 	      /* Next highest register to be saved.  */
 	      mem2 = gen_mem_ref (DFmode,
 				  plus_constant
@@ -1964,10 +1965,10 @@  aarch64_save_or_restore_fprs (int start_offset, int increment,
 				gen_rtx_REG (DFmode, regno2));
 		}
 
-		  /* The first part of a frame-related parallel insn
-		     is always assumed to be relevant to the frame
-		     calculations; subsequent parts, are only
-		     frame-related if explicitly marked.  */
+	      /* The first part of a frame-related parallel insn is
+		 always assumed to be relevant to the frame
+		 calculations; subsequent parts, are only
+		 frame-related if explicitly marked.  */
 	      RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
 	      regno = regno2;
 	      start_offset += increment * 2;
@@ -1987,15 +1988,14 @@  aarch64_save_or_restore_fprs (int start_offset, int increment,
 	  RTX_FRAME_RELATED_P (insn) = 1;
 	}
     }
-
 }
 
 
 /* offset from the stack pointer of where the saves and
    restore's have to happen.  */
 static void
-aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
-					    bool restore)
+aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT start_offset,
+					       bool restore)
 {
   rtx insn;
   rtx base_rtx = stack_pointer_rtx;
@@ -2027,6 +2027,7 @@  aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
 	      aarch64_register_saved_on_entry (regno2))
 	    {
 	      rtx mem2;
+
 	      /* Next highest register to be saved.  */
 	      mem2 = gen_mem_ref (Pmode,
 				  plus_constant
@@ -2050,12 +2051,11 @@  aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
 		  add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno2));
 		}
 
-		  /* The first part of a frame-related parallel insn
-		     is always assumed to be relevant to the frame
-		     calculations; subsequent parts, are only
-		     frame-related if explicitly marked.  */
-	      RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0,
-					    1)) = 1;
+	      /* The first part of a frame-related parallel insn is
+		 always assumed to be relevant to the frame
+		 calculations; subsequent parts, are only
+		 frame-related if explicitly marked.  */
+	      RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
 	      regno = regno2;
 	      start_offset += increment * 2;
 	    }
@@ -2075,7 +2075,6 @@  aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
     }
 
   aarch64_save_or_restore_fprs (start_offset, increment, restore, base_rtx);
-
 }
 
 /* AArch64 stack frames generated by this compiler look like: