Patchwork * mpc8313erdb.dts: Fixed eTSEC interrupt assignment.

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Submitter Kim Phillips
Date Oct. 12, 2009, 4:06 p.m.
Message ID <20091012110619.972d0f61.kim.phillips@freescale.com>
Download mbox | patch
Permalink /patch/35785/
State Deferred
Delegated to: Kumar Gala
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Comments

Kim Phillips - Oct. 12, 2009, 4:06 p.m.
On Wed, 9 Sep 2009 15:28:01 -0500
Kumar Gala <galak@kernel.crashing.org> wrote:

> 
> On Sep 9, 2009, at 1:22 PM, Scott Wood wrote:
> 
> > On Fri, Sep 04, 2009 at 12:31:25PM +0200, Roland Lezuo wrote:
> >> The following patch is needed to correctly assign the IRQs for the
> >> gianfar driver on the MPC8313ERDB-revc boards. ERR and TX are swapped
> >> as well as the interrupt lines for the two devices.
> >
> > And it will incorrectly assign them on older revisions of the chip.
> >
> > We really should have a u-boot fixup based on SVR.

Roland, is it possible for you to test this u-boot patch?:

From 44c73137acf20626e930e3f4142e60054d8bd46f Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Mon, 12 Oct 2009 10:51:20 -0500
Subject: [PATCH] mpc83xx: mpc8313 - handle erratum IPIC1 (TSEC IRQ number swappage)

mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
h/w (see AN3545).  The base device tree in use has rev. 1 ID numbers,
so if on Rev. 2 (and higher) h/w, we fix them up here.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 cpu/mpc83xx/fdt.c |   39 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 39 insertions(+), 0 deletions(-)
Kim Phillips - Oct. 16, 2009, 10:27 p.m.
On Thu, 15 Oct 2009 21:40:43 +0200
Roland Lezuo <roland.lezuo@chello.at> wrote:

> On Mon, 2009-10-12 at 11:06 -0500, Kim Phillips wrote:
> > On Wed, 9 Sep 2009 15:28:01 -0500
> > Kumar Gala <galak@kernel.crashing.org> wrote:
> > > On Sep 9, 2009, at 1:22 PM, Scott Wood wrote:
> > > > We really should have a u-boot fixup based on SVR.
> > 
> > Roland, is it possible for you to test this u-boot patch?:
> 
> No sorry, I have no MPC8313ERDB at hands. But the patch at least looks
> good...

ok, thanks - I went ahead and applied it anyway; it'll be tested by
the next u-boot release.  I've added your reviewed-by.

Kim

Patch

diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c
index 13443cb..daf73a6 100644
--- a/cpu/mpc83xx/fdt.c
+++ b/cpu/mpc83xx/fdt.c
@@ -69,6 +69,45 @@  void ft_cpu_setup(void *blob, bd_t *bd)
     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
     defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
 	fdt_fixup_ethernet(blob);
+#ifdef CONFIG_MPC8313
+	/*
+	* mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
+	* h/w (see AN3545).  The base device tree in use has rev. 1 ID numbers,
+	* so if on Rev. 2 (and higher) h/w, we fix them up here
+	*/
+	if (REVID_MAJOR(immr->sysconf.spridr) >= 2) {
+		int nodeoffset, path;
+		const char *prop;
+
+		nodeoffset = fdt_path_offset(blob, "/aliases");
+		if (nodeoffset >= 0) {
+#if defined(CONFIG_HAS_ETH0)
+			prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
+			if (prop) {
+				u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
+
+				path = fdt_path_offset(blob, prop);
+				prop = fdt_getprop(blob, path, "interrupts", 0);
+				if (prop)
+					fdt_setprop(blob, path, "interrupts",
+						    &tmp, sizeof(tmp));
+			}
+#endif
+#if defined(CONFIG_HAS_ETH1)
+			prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
+			if (prop) {
+				u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
+
+				path = fdt_path_offset(blob, prop);
+				prop = fdt_getprop(blob, path, "interrupts", 0);
+				if (prop)
+					fdt_setprop(blob, path, "interrupts",
+						    &tmp, sizeof(tmp));
+			}
+#endif
+		}
+	}
+#endif
 #endif
 
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,