@@ -598,6 +598,12 @@ union ring_type {
#define PHY_BCM54XX_SHD_WRITE 0x8000
#define PHY_BCM54XX_SHD_REG3 0x0c00 /* shadow reg 3 - unknown */
+/* AC131: */
+#define PHY_BCM_AC131_BRCMTEST 0x1f /* Brcm test register */
+#define PHY_BCM_AC131_BRCMTEST_SRE 0x0080 /* Shadow register enable */
+#define PHY_BCM_AC131_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
+#define PHY_BCM_AC131_SHDW_AUXSTAT2_APDE 0x0020 /* Auto power down enable */
+
#define PHY_GIGABIT 0x0100
#define PHY_TIMEOUT 0x1
@@ -1415,6 +1421,23 @@ static int phy_init(struct net_device *dev)
}
if (np->phy_oui == PHY_OUI_BROADCOM) {
+ if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
+ if (np->phy_model == PHY_MODEL_BROADCOM_AC131) {
+ phy_reserved = mii_rw(dev, np->phyaddr, PHY_BCM_AC131_BRCMTEST, MII_READ);
+ phy_reserved |= PHY_BCM_AC131_BRCMTEST_SRE;
+ if (mii_rw(dev, np->phyaddr, PHY_BCM_AC131_BRCMTEST,phy_reserved)) {
+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+ return PHY_ERROR;
+ }
+
+ phy_reserved = mii_rw(dev, np->phyaddr, PHY_BCM_AC131_SHDW_AUXSTAT2, MII_READ);
+ phy_reserved |= PHY_BCM_AC131_SHDW_AUXSTAT2_APDE;
+ if (mii_rw(dev, np->phyaddr, PHY_BCM_AC131_SHDW_AUXSTAT2,phy_reserved)) {
+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+ return PHY_ERROR;
+ }
+ }
+ }
if (np->phy_model == PHY_MODEL_BROADCOM_50610) {
if (mii_rw(dev, np->phyaddr, PHY_BCM54XX_SHD, PHY_BCM54XX_SHD_WRITE||
PHY_BCM54XX_SHD_REG3|0)) {