[RESEND,02/12] clk: st: Adds Flexgen clock binding
diff mbox

Message ID 1401892320-18211-3-git-send-email-gabriel.fernandez@linaro.org
State Superseded, archived
Headers show

Commit Message

Gabriel Fernandez June 4, 2014, 2:31 p.m. UTC
A Flexgen structure is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
 .../devicetree/bindings/clock/st/st,clkgen.txt     |  5 +++
 .../devicetree/bindings/clock/st/st,flexgen.txt    | 48 ++++++++++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/st/st,flexgen.txt

Comments

Peter Griffin June 5, 2014, 7:51 a.m. UTC | #1
Hi Gabi,

> +Example:
> +
> +	clockgenD2@x9106000 {
> +		compatible = "st,clkgen-c32";
> +		reg = <0x9106000 0x1000>;
> +
> +		CLK_S_D2_FLEXGEN: CLK_S_D2_FLEXGEN {
> +			compatible = "st,flexgen";
> +
> +			#clock-cells = <1>;
> +			clocks = <&CLK_S_D2_QUADFS 0>,
> +				 <&CLK_S_D2_QUADFS 1>,
> +				 <&CLK_S_D2_QUADFS 2>,
> +				 <&CLK_S_D2_QUADFS 3>;
> +
> +			clock-output-names = "CLK_PIX_MAIN_DISP",
> +					     "CLK_PIX_PIP",
> +					     "CLK_PIX_GDP1",
> +					     "CLK_PIX_GDP2";

With the upper case to lower case renaming of the STI device tree
this example also needs to be converted to lower case names 
throughout.

Once rectified you can add my:
 Acked-by: Peter Griffin <peter.griffin@linaro.org>

regards,

Peter.

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Patch
diff mbox

diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
index 55506c2..afb65e6 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -32,6 +32,10 @@  address is common of all subnode.
 		vcc_node {
 			...
 		};
+
+		flexgen_node {
+			...
+		};
 		...
 	};
 
@@ -45,6 +49,7 @@  Each subnode should use the binding discribe in [2]..[7]
 [5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
 [6] Documentation/devicetree/bindings/clock/st,vcc.txt
 [7] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
 
 
 Required properties:
diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
new file mode 100644
index 0000000..ce908dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
@@ -0,0 +1,48 @@ 
+Binding for a type of flexgen structure found on certain
+STMicroelectronics consumer electronics SoC devices
+
+This structure includes:
+- a clock cross bar (represented by a mux element)
+- a pre and final dividers (represented by a divider and gate elements)
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be:
+  "st,flexgen"
+
+- #clock-cells : from common clock binding; shall be set to 1.
+
+- clocks : from common clock binding
+
+- clock-output-names : From common clock binding. The block has 4
+                       clock outputs but not all of them in a specific instance
+                       have to be used in the SoC. If a clock name is left as
+                       an empty string then no clock will be created for the
+                       output associated with that string index. If fewer than
+                       4 strings are provided then no clocks will be created
+                       for the remaining outputs.
+
+Example:
+
+	clockgenD2@x9106000 {
+		compatible = "st,clkgen-c32";
+		reg = <0x9106000 0x1000>;
+
+		CLK_S_D2_FLEXGEN: CLK_S_D2_FLEXGEN {
+			compatible = "st,flexgen";
+
+			#clock-cells = <1>;
+			clocks = <&CLK_S_D2_QUADFS 0>,
+				 <&CLK_S_D2_QUADFS 1>,
+				 <&CLK_S_D2_QUADFS 2>,
+				 <&CLK_S_D2_QUADFS 3>;
+
+			clock-output-names = "CLK_PIX_MAIN_DISP",
+					     "CLK_PIX_PIP",
+					     "CLK_PIX_GDP1",
+					     "CLK_PIX_GDP2";
+		};
+	};