diff mbox

[v5,20/30] target-ppc: Add POWER8's TIR SPR

Message ID 1401886265-6589-21-git-send-email-aik@ozlabs.ru
State New
Headers show

Commit Message

Alexey Kardashevskiy June 4, 2014, 12:50 p.m. UTC 
This adds TIR (Thread Identification Register) SPR first defined for server
CPUs in PowerISA 2.07.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v5:
* TIR is defined for servers from 2.07 so it is power8 only

v4:
* disabled reading it from user space
---
 target-ppc/cpu.h            |  1 +
 target-ppc/translate_init.c | 10 ++++++++++
 2 files changed, 11 insertions(+)

Comments

Tom Musta June 4, 2014, 5:29 p.m. UTC | #1 
On 6/4/2014 7:50 AM, Alexey Kardashevskiy wrote:
> This adds TIR (Thread Identification Register) SPR first defined for server
> CPUs in PowerISA 2.07.
> 
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> Changes:
> v5:
> * TIR is defined for servers from 2.07 so it is power8 only
> 
> v4:
> * disabled reading it from user space
> ---
>  target-ppc/cpu.h            |  1 +
>  target-ppc/translate_init.c | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 8955f29..3a578e6 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1374,6 +1374,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>  #define SPR_BOOKE_GIVOR8      (0x1BB)
>  #define SPR_BOOKE_GIVOR13     (0x1BC)
>  #define SPR_BOOKE_GIVOR14     (0x1BD)
> +#define SPR_TIR               (0x1BE)
>  #define SPR_BOOKE_SPEFSCR     (0x200)
>  #define SPR_Exxx_BBEAR        (0x201)
>  #define SPR_Exxx_BBTAR        (0x202)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 7eb02ac..1df69e0 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7518,6 +7518,15 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
>                   0x00000000);
>  }
>  
> +static void gen_spr_power8_ids(CPUPPCState *env)
> +{
> +    /* Thread identification */
> +    spr_register(env, SPR_TIR, "TIR",
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_generic, SPR_NOACCESS,
> +                 0x00000000);
> +}
> +
>  static void gen_spr_book3s_purr(CPUPPCState *env)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> @@ -7621,6 +7630,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>      }
>      if (version >= BOOK3S_CPU_POWER8) {
>          gen_spr_power8_tce_address_control(env);
> +        gen_spr_power8_ids(env);
>      }
>  #if !defined(CONFIG_USER_ONLY)
>      switch (version) {
> 
Reviewed-by: Tom Musta <tommusta@gmail.com>
diff mbox

Patch

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8955f29..3a578e6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1374,6 +1374,7 @@  static inline int cpu_mmu_index (CPUPPCState *env)
 #define SPR_BOOKE_GIVOR8      (0x1BB)
 #define SPR_BOOKE_GIVOR13     (0x1BC)
 #define SPR_BOOKE_GIVOR14     (0x1BD)
+#define SPR_TIR               (0x1BE)
 #define SPR_BOOKE_SPEFSCR     (0x200)
 #define SPR_Exxx_BBEAR        (0x201)
 #define SPR_Exxx_BBTAR        (0x202)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7eb02ac..1df69e0 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7518,6 +7518,15 @@  static void gen_spr_book3s_ids(CPUPPCState *env)
                  0x00000000);
 }
 
+static void gen_spr_power8_ids(CPUPPCState *env)
+{
+    /* Thread identification */
+    spr_register(env, SPR_TIR, "TIR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, SPR_NOACCESS,
+                 0x00000000);
+}
+
 static void gen_spr_book3s_purr(CPUPPCState *env)
 {
 #if !defined(CONFIG_USER_ONLY)
@@ -7621,6 +7630,7 @@  static void init_proc_book3s_64(CPUPPCState *env, int version)
     }
     if (version >= BOOK3S_CPU_POWER8) {
         gen_spr_power8_tce_address_control(env);
+        gen_spr_power8_ids(env);
     }
 #if !defined(CONFIG_USER_ONLY)
     switch (version) {