===================================================================
@@ -111,6 +111,7 @@
UNSPEC_LEA_ADDR
UNSPEC_XBEGIN_ABORT
UNSPEC_STOS
+ UNSPEC_PEEPSIB
;; For SSE/MMX support:
UNSPEC_FIX_NOTRUNC
@@ -11382,6 +11383,61 @@
"* return ix86_output_call_insn (insn, operands[0]);"
[(set_attr "type" "call")])
+(define_insn "*sibcall_intern"
+ [(call (unspec [(mem:QI (match_operand:W 0 "memory_operand"))]
UNSPEC_PEEPSIB)
+ (match_operand 1))]
+ ""
+ "* return ix86_output_call_insn (insn, operands[0]);"
+ [(set_attr "type" "call")])
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "memory_operand"))
+ (call (mem:QI (match_operand:DI 2 "register_operand"))
+ (match_operand 3))]
+ "TARGET_64BIT && REG_P (operands[0])
+ && REG_P (operands[2])
+ && SIBLING_CALL_P (peep2_next_insn (1))
+ && REGNO (operands[0]) == REGNO (operands[2])"
+ [(call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB) (match_dup 3))])
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "memory_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (call (mem:QI (match_operand:DI 2 "register_operand"))
+ (match_operand 3))]
+ "TARGET_64BIT && REG_P (operands[0])
+ && REG_P (operands[2])
+ && SIBLING_CALL_P (peep2_next_insn (2))
+ && REGNO (operands[0]) == REGNO (operands[2])"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB) (match_dup 3))])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_operand"))
+ (call (mem:QI (match_operand:SI 2 "register_operand"))
+ (match_operand 3))]
+ "!TARGET_64BIT && REG_P (operands[0])
+ && REG_P (operands[2])
+ && SIBLING_CALL_P (peep2_next_insn (1))
+ && REGNO (operands[0]) == REGNO (operands[2])"
+ [(call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB) (match_dup 3))])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (call (mem:QI (match_operand:SI 2 "register_operand"))
+ (match_operand 3))]
+ "!TARGET_64BIT && REG_P (operands[0])
+ && REG_P (operands[2])
+ && SIBLING_CALL_P (peep2_next_insn (2))
+ && REGNO (operands[0]) == REGNO (operands[2])"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB) (match_dup 3))])
+
(define_expand "call_pop"
[(parallel [(call (match_operand:QI 0)