From patchwork Wed Jun 4 11:32:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 355858 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A18EE14009C for ; Wed, 4 Jun 2014 21:49:37 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752482AbaFDLrk (ORCPT ); Wed, 4 Jun 2014 07:47:40 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:10022 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752776AbaFDLri (ORCPT ); Wed, 4 Jun 2014 07:47:38 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 04 Jun 2014 04:47:10 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 04 Jun 2014 04:42:29 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 04 Jun 2014 04:42:29 -0700 Received: from mperttunen-lnx.Nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Wed, 4 Jun 2014 04:47:37 -0700 From: Mikko Perttunen To: , , , CC: , , , , Mikko Perttunen Subject: [PATCH 4/9] clk: tegra: Enable hardware control of SATA PLL Date: Wed, 4 Jun 2014 14:32:34 +0300 Message-ID: <1401881559-18469-5-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1401881559-18469-1-git-send-email-mperttunen@nvidia.com> References: <1401881559-18469-1-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This makes the SATA PLL be controlled by hardware instead of software. This is required for working SATA support. Signed-off-by: Mikko Perttunen Acked-by: Stephen Warren --- drivers/clk/tegra/clk-pll.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 637b62c..f070c36 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -110,6 +110,9 @@ #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) +#define SATA_PLL_CFG0 0x490 +#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) + #define PLLE_MISC_PLLE_PTS BIT(8) #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) @@ -1361,6 +1364,11 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; pll_writel(val, XUSBIO_PLL_CFG0, pll); + /* Enable hw control of SATA pll */ + val = pll_readl(SATA_PLL_CFG0, pll); + val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; + pll_writel(val, SATA_PLL_CFG0, pll); + out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags);