| Message ID | 1401881559-18469-5-git-send-email-mperttunen@nvidia.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On 06/04/2014 05:32 AM, Mikko Perttunen wrote: > This makes the SATA PLL be controlled by hardware instead of software. > This is required for working SATA support. Peter, could you please take patches 4 and 5 through the clock tree. As far as I can tell, there's no compile-time dependency in the clock patches, so they can go through a different tree to the rest of the series without issue. These 2 patches look fine to me, so consider them: Acked-by: Stephen Warren <swarren@nvidia.com> -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Jun 16, 2014 at 11:49:18PM +0200, Stephen Warren wrote: > On 06/04/2014 05:32 AM, Mikko Perttunen wrote: > > This makes the SATA PLL be controlled by hardware instead of software. > > This is required for working SATA support. > > Peter, could you please take patches 4 and 5 through the clock tree. As > far as I can tell, there's no compile-time dependency in the clock > patches, so they can go through a different tree to the rest of the > series without issue. These 2 patches look fine to me, so consider them: > > Acked-by: Stephen Warren <swarren@nvidia.com> Ok. Will do. Cheers, Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 637b62c..f070c36 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -110,6 +110,9 @@ #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) +#define SATA_PLL_CFG0 0x490 +#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) + #define PLLE_MISC_PLLE_PTS BIT(8) #define PLLE_MISC_IDDQ_SW_VALUE BIT(13) #define PLLE_MISC_IDDQ_SW_CTRL BIT(14) @@ -1361,6 +1364,11 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; pll_writel(val, XUSBIO_PLL_CFG0, pll); + /* Enable hw control of SATA pll */ + val = pll_readl(SATA_PLL_CFG0, pll); + val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; + pll_writel(val, SATA_PLL_CFG0, pll); + out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags);
This makes the SATA PLL be controlled by hardware instead of software. This is required for working SATA support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> --- drivers/clk/tegra/clk-pll.c | 8 ++++++++ 1 file changed, 8 insertions(+)