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[U-Boot,v2,5/5] Exynos: Split 5250 and 5420 memory bank configuration

Message ID 1401799074-3801-6-git-send-email-akshay.s@samsung.com
State Superseded
Delegated to: Minkyu Kang
Headers show

Commit Message

Akshay Saraswat June 3, 2014, 12:37 p.m. UTC 
From: Michael Pratt <mpratt@chromium.org>

Since snow has a different memory configuration than peach, split the
configuration between the 5250 and 5420. Exynos 5420 supports runtime
memory configuration detection, and can make the determination between 4
and 7 banks at runtime.

Include the bank size with the number of banks for context to make the
number of banks meaningful.

Signed-off-by: Michael Pratt <mpratt@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
Changes since v1:
	- New patch.

 include/configs/exynos5-dt.h    | 2 --
 include/configs/exynos5250-dt.h | 5 +++++
 include/configs/exynos5420.h    | 4 ++++
 3 files changed, 9 insertions(+), 2 deletions(-)

Comments

Simon Glass June 3, 2014, 2:30 p.m. UTC | #1 
On 3 June 2014 06:37, Akshay Saraswat <akshay.s@samsung.com> wrote:
> From: Michael Pratt <mpratt@chromium.org>
>
> Since snow has a different memory configuration than peach, split the
> configuration between the 5250 and 5420. Exynos 5420 supports runtime
> memory configuration detection, and can make the determination between 4
> and 7 banks at runtime.
>
> Include the bank size with the number of banks for context to make the
> number of banks meaningful.
>
> Signed-off-by: Michael Pratt <mpratt@chromium.org>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>

Acked-by: Simon Glass <sjg@chromium.org>
Tested on 2GB pit
Tested-by: Simon Glass <sjg@chromium.org>
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Patch

diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h
index d3ef44c..fd607ee 100644
--- a/include/configs/exynos5-dt.h
+++ b/include/configs/exynos5-dt.h
@@ -161,8 +161,6 @@ 
 
 #define CONFIG_RD_LVL
 
-#define CONFIG_NR_DRAM_BANKS	8
-#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 10b8942..27aa455 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -65,4 +65,9 @@ 
 #define LCD_YRES			1600
 #define LCD_BPP			LCD_COLOR16
 #endif
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
 #endif  /* __CONFIG_5250_H */
diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h
index 2ffe5ee..d2a9556 100644
--- a/include/configs/exynos5420.h
+++ b/include/configs/exynos5420.h
@@ -45,4 +45,8 @@ 
  */
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
 
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	7
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+
 #endif	/* __CONFIG_EXYNOS5420_H */