| Message ID | 1401779120-20306-3-git-send-email-rainer.boschung@keymile.com |
|---|---|
| State | Accepted |
| Delegated to: | York Sun |
| Headers | show |
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote: > For e500mc cores the watchdog timer period has to be set by means of a > 6bit value, that defines the bit of the timebase counter used to signal > a watchdog timer exception on its 0 to 1 transition. > The macro used to set the watchdog period TCR_WP, was redefined for e500mc > to support 6 WP setting. > > The parameter (x) given to the macro specifies the prescaling factor of > the time base clock (fTB): > > watchdog_period = 1/fTB * 2^x > > Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> > --- > arch/powerpc/include/asm/processor.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h > index edd7375..f32aa66 100644 > --- a/arch/powerpc/include/asm/processor.h > +++ b/arch/powerpc/include/asm/processor.h > @@ -378,11 +378,16 @@ > #else > #define SPRN_TCR 0x154 /* Book E Timer Control Register */ > #endif /* CONFIG_BOOKE */ > +#ifdef CONFIG_E500MC > +#define TCR_WP(x) (((64-x)&0x3)<<30)| \ > + (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/ > +#else > #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ This applies to all e500, not just e500mc and derivatives. > #define WP_2_17 0 /* 2^17 clocks */ > #define WP_2_21 1 /* 2^21 clocks */ > #define WP_2_25 2 /* 2^25 clocks */ > #define WP_2_29 3 /* 2^29 clocks */ > +#endif /* CONFIG_E500 */ Comment doesn't match #ifdef -Scott
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index edd7375..f32aa66 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -378,11 +378,16 @@ #else #define SPRN_TCR 0x154 /* Book E Timer Control Register */ #endif /* CONFIG_BOOKE */ +#ifdef CONFIG_E500MC +#define TCR_WP(x) (((64-x)&0x3)<<30)| \ + (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/ +#else #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ #define WP_2_17 0 /* 2^17 clocks */ #define WP_2_21 1 /* 2^21 clocks */ #define WP_2_25 2 /* 2^25 clocks */ #define WP_2_29 3 /* 2^29 clocks */ +#endif /* CONFIG_E500 */ #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ #define WRC_NONE 0 /* No reset will occur */ #define WRC_CORE 1 /* Core reset will occur */
For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> --- arch/powerpc/include/asm/processor.h | 5 +++++ 1 file changed, 5 insertions(+)