From patchwork Fri May 30 11:20:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 354086 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B89BC1400D6 for ; Fri, 30 May 2014 21:20:52 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754906AbaE3LUt (ORCPT ); Fri, 30 May 2014 07:20:49 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12088 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752059AbaE3LUr (ORCPT ); Fri, 30 May 2014 07:20:47 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 30 May 2014 04:21:05 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 30 May 2014 04:15:43 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 30 May 2014 04:15:43 -0700 Received: from deemhub02.nvidia.com (10.21.69.138) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.342.0; Fri, 30 May 2014 04:20:46 -0700 Received: from oreo.nvidia.com (10.21.65.27) by deemhub02.nvidia.com (10.21.69.138) with Microsoft SMTP Server (TLS) id 8.3.342.0; Fri, 30 May 2014 13:20:43 +0200 From: Hiroshi Doyu To: Subject: [PATCHv8 14/21] iommu/tegra124: smmu: convert swgroup ID to asid offset Date: Fri, 30 May 2014 14:20:27 +0300 Message-ID: <1401448834-32659-15-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 2.0.0.rc1.15.g7e76a2f In-Reply-To: <1401448834-32659-1-git-send-email-hdoyu@nvidia.com> References: <1401448834-32659-1-git-send-email-hdoyu@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Provide a conversion table from swgroup ID to MC_SMMU__ASID_0 register offset to support non-linear conversion. This conversion used to be exactly linear but after T124 we need a conversion table to support non-linear cases. We would also need another table to convert swgroup ID to HOTRESET bit. Signed-off-by: Hiroshi Doyu --- drivers/iommu/tegra-smmu.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 20dddc305fb2..080dbda874e5 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -184,8 +184,6 @@ enum { #define __smmu_client_enable_swgroups(c, m) __smmu_client_set_swgroups(c, m, 1) #define __smmu_client_disable_swgroups(c) __smmu_client_set_swgroups(c, 0, 0) -#define SWGROUPS_ASID_REG(x) ((x) * sizeof(u32) + SMMU_ASID_BASE) - /* * Per client for address space */ @@ -314,6 +312,23 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) */ #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG) +static size_t smmu_get_asid_offset(int id) +{ + switch (id) { + case TEGRA_SWGROUP_DC14: + return 0x490; + case TEGRA_SWGROUP_DC12: + return 0xa88; + case TEGRA_SWGROUP_AFI...TEGRA_SWGROUP_ISP: + case TEGRA_SWGROUP_MPE...TEGRA_SWGROUP_PPCS1: + return (id - TEGRA_SWGROUP_AFI) * sizeof(u32) + SMMU_ASID_BASE; + case TEGRA_SWGROUP_SDMMC1A...63: + return (id - TEGRA_SWGROUP_SDMMC1A) * sizeof(u32) + 0xa94; + }; + + BUG(); +} + static struct smmu_client *find_smmu_client(struct smmu_device *smmu, struct device_node *dev_node) { @@ -415,7 +430,7 @@ static int __smmu_client_set_swgroups(struct smmu_client *c, map = c->swgroups; for_each_set_bit(i, map, TEGRA_SWGROUP_MAX) { - offs = SWGROUPS_ASID_REG(i); + offs = smmu_get_asid_offset(i); val = smmu_read(smmu, offs); if (on) { if (val) {