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[U-Boot,7/9] driver/ddr/freescale: Fix DDR3 driver for ARM

Message ID 1401434582-18032-8-git-send-email-b18965@freescale.com
State Superseded
Delegated to: York Sun
Headers show

Commit Message

Alison Wang May 30, 2014, 7:23 a.m. UTC 
From: York Sun <yorksun@freescale.com>

Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index d4ed9ae..59f2fd6 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -194,7 +194,7 @@  step2:
 	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 	 * Let's wait for 800ms
 	 */
-	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 		(get_ddr_freq(0) >> 20)) << 1;