@@ -217,6 +217,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
* IOAPIC RTE entries, so we just enable RTE for the device.
*/
+ if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0)
+ return -EBUSY;
+
irq_attr.ioapic = mp_find_ioapic(dev->irq);
irq_attr.ioapic_pin = dev->irq;
irq_attr.trigger = 1; /* level */
@@ -473,6 +473,8 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
/* PNW and CLV go with active low */
irq_attr.polarity = 1;
}
+ WARN_ON(mp_map_gsi_to_irq(irq,
+ IOAPIC_MAP_ALLOC) < 0);
io_apic_set_pci_routing(NULL, irq, &irq_attr);
}
} else {
@@ -25,6 +25,7 @@
#include <linux/init.h>
#include <linux/sfi.h>
#include <linux/io.h>
+#include <linux/irqdomain.h>
#include <asm/io_apic.h>
#include <asm/mpspec.h>
@@ -70,6 +71,13 @@ static int __init sfi_parse_cpus(struct sfi_table_header *table)
#endif /* CONFIG_X86_LOCAL_APIC */
#ifdef CONFIG_X86_IO_APIC
+static struct irq_domain_ops sfi_ioapic_irqdomain_ops;
+
+static struct irq_domain *sfi_ioapic_create_irqdomain(int ioapic, void *arg)
+{
+ ioapic_identity_map = 1;
+ return mp_irqdomain_create(ioapic, NULL, &sfi_ioapic_irqdomain_ops);
+}
static int __init sfi_parse_ioapic(struct sfi_table_header *table)
{
@@ -82,7 +90,8 @@ static int __init sfi_parse_ioapic(struct sfi_table_header *table)
pentry = (struct sfi_apic_table_entry *)sb->pentry;
for (i = 0; i < num; i++) {
- mp_register_ioapic(i, pentry->phys_addr, gsi_top, NULL, NULL);
+ mp_register_ioapic(i, pentry->phys_addr, gsi_top,
+ sfi_ioapic_create_irqdomain, NULL);
pentry++;
}
Enhance SFI to provide basic support of irqdomain with identity mapping between GSIs and IRQs. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> --- arch/x86/pci/intel_mid_pci.c | 3 +++ arch/x86/platform/intel-mid/sfi.c | 2 ++ arch/x86/platform/sfi/sfi.c | 11 ++++++++++- 3 files changed, 15 insertions(+), 1 deletion(-)