diff mbox

[U-Boot,1/4] Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init

Message ID 1400751158-400-1-git-send-email-akshay.s@samsung.com
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Commit Message

Akshay Saraswat May 22, 2014, 9:32 a.m. UTC 
Passing fewer arguments is better and mem_iv_size is never
used. Let's keep only one argument and make it cleaner.

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
 arch/arm/cpu/armv7/exynos/dmc_common.c    |  5 +----
 arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 10 ++++++----
 arch/arm/cpu/armv7/exynos/exynos5_setup.h |  8 +-------
 3 files changed, 8 insertions(+), 15 deletions(-)

Comments

Simon Glass May 23, 2014, 11:21 p.m. UTC | #1 
Hi Akshay,

On 21 May 2014 23:32, Akshay Saraswat <akshay.s@samsung.com> wrote:
> Passing fewer arguments is better and mem_iv_size is never
> used. Let's keep only one argument and make it cleaner.

I agree with removing mem_iv_size as it is not used. But all you are
doing with the other parameter is making the called function look it
up again. I'm not sure that is a win. It doesn't reduce code size.
(see commit 05 - there is no change).

./tools/buildman/buildman -b try-pit smdk5420 -sS
Summary of 8 commits for 2 boards (2 threads, 2 jobs per thread)
01: ARM: exynos5420: removed undefined gpio structure
       arm: +   peach-pit
02: Exynos5420: Introduce support for the Peach-Pit board
03: Exynos5420: Let macros be used for exynos5420
       arm:    peach-pit
04: Exynos: Make sure ps_hold gets set in the SPL
       arm: (for 2/2 boards)  spl/u-boot-spl:all +72.0
spl/u-boot-spl:text +72.0
05: Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init
06: Exynos5420: Remove code for enabling read leveling
       arm: (for 2/2 boards)  spl/u-boot-spl:all -344.0
spl/u-boot-spl:text -344.0
07: DMC: exynos5420: Gate CLKM to when reading PHY_CON13
       arm: (for 2/2 boards)  spl/u-boot-spl:all +136.0
spl/u-boot-spl:text +136.0
08: Exynos5420: DMC: Add software read leveling
       arm: (for 2/2 boards)  spl/u-boot-spl:all +712.0
spl/u-boot-spl:rodata +16.0  spl/u-boot-spl:text +696.0
(try-pit=9276cf: b/ fred.dtb mdk5420 sandbox/ scripts/ x) ~/u>

Anyway it doesn't hurt, so:

Acked-by: Simon Glass <sjg@chromium.org>

>
> Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> ---

Regards,
Simon
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c
index cca925e..acc9e25 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_common.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
@@ -155,14 +155,11 @@  void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd)
 void mem_ctrl_init(int reset)
 {
 	struct spl_machine_param *param = spl_get_machine_params();
-	struct mem_timings *mem;
 	int ret;
 
-	mem = clock_get_mem_timings();
-
 	/* If there are any other memory variant, add their init call below */
 	if (param->mem_type == DDR_MODE_DDR3) {
-		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
+		ret = ddr3_mem_ctrl_init(reset);
 		if (ret) {
 			/* will hang if failed to init memory control */
 			while (1)
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 487e6f4..a89930b 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -28,18 +28,19 @@  static void reset_phy_ctrl(void)
 	writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-		       int reset)
+int ddr3_mem_ctrl_init(int reset)
 {
 	unsigned int val;
 	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
 	struct exynos5_dmc *dmc;
+	struct mem_timings *mem;
 	int i;
 
 	phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
 	phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
 							+ DMC_OFFSET);
 	dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
+	mem = clock_get_mem_timings();
 
 	if (reset)
 		reset_phy_ctrl();
@@ -221,8 +222,7 @@  int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 #endif
 
 #ifdef CONFIG_EXYNOS5420
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-		       int reset)
+int ddr3_mem_ctrl_init(int reset)
 {
 	struct exynos5420_clock *clk =
 		(struct exynos5420_clock *)samsung_get_base_clock();
@@ -231,6 +231,7 @@  int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
 	struct exynos5420_dmc *drex0, *drex1;
 	struct exynos5420_tzasc *tzasc0, *tzasc1;
+	struct mem_timings *mem;
 	uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
 	int chip;
 	int i;
@@ -244,6 +245,7 @@  int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
 	tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
 							+ DMC_OFFSET);
+	mem = clock_get_mem_timings();
 
 	/* Enable PAUSE for DREX */
 	setbits_le32(&clk->pause, ENABLE_BIT);
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 53b0ace..b50af2f 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -890,16 +890,10 @@  enum {
 /*
  * Memory variant specific initialization code for DDR3
  *
- * @param mem		Memory timings for this memory type.
- * @param mem_iv_size	Memory interleaving size is a configurable parameter
- *			which the DMC uses to decide how to split a memory
- *			chunk into smaller chunks to support concurrent
- *			accesses; may vary across boards.
  * @param reset         Reset DDR PHY during initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-			int reset);
+int ddr3_mem_ctrl_init(int reset);
 
 /* Memory variant specific initialization code for LPDDR3 */
 void lpddr3_mem_ctrl_init(void);