| Message ID | 1400491383-6725-10-git-send-email-edgar.iglesias@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 19 May 2014 10:22, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Add aarch64_banked_spsr_index(), used to map an Exception Level > to an index in the banked_spsr array. > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index f120b02..c05a839 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -386,7 +386,8 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) > > void HELPER(exception_return)(CPUARMState *env) > { > - uint32_t spsr = env->banked_spsr[0]; > + unsigned int spsr_idx = is_a64(env) ? aarch64_banked_spsr_index(1) : 0; This is unnecessary -- if we get here we must have is_a64(env) true, because this is the helper for an A64 instruction. > + uint32_t spsr = env->banked_spsr[spsr_idx]; > int new_el, i; > > if (env->pstate & PSTATE_SP) { thanks -- PMM
On Wed, May 21, 2014 at 08:01:54PM +0100, Peter Maydell wrote: > On 19 May 2014 10:22, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > > > Add aarch64_banked_spsr_index(), used to map an Exception Level > > to an index in the banked_spsr array. > > > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > > index f120b02..c05a839 100644 > > --- a/target-arm/op_helper.c > > +++ b/target-arm/op_helper.c > > @@ -386,7 +386,8 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) > > > > void HELPER(exception_return)(CPUARMState *env) > > { > > - uint32_t spsr = env->banked_spsr[0]; > > + unsigned int spsr_idx = is_a64(env) ? aarch64_banked_spsr_index(1) : 0; > > This is unnecessary -- if we get here we must have is_a64(env) true, > because this is the helper for an A64 instruction. Yep, got confused while your previous comments. Fixed > > > + uint32_t spsr = env->banked_spsr[spsr_idx]; > > int new_el, i; > > > > if (env->pstate & PSTATE_SP) { > > thanks > -- PMM
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index b8e6d56..b970fd1 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -488,7 +488,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } if (is_a64(env)) { - env->banked_spsr[0] = pstate_read(env); + env->banked_spsr[aarch64_banked_spsr_index(1)] = pstate_read(env); env->sp_el[arm_current_pl(env)] = env->xregs[31]; env->xregs[31] = env->sp_el[1]; env->elr_el[1] = env->pc; diff --git a/target-arm/internals.h b/target-arm/internals.h index d63a975..c9897c2 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -75,6 +75,20 @@ static inline void arm_log_exception(int idx) */ #define GTIMER_SCALE 16 +/* + * For AArch64, map a given EL to an index in the banked_spsr array. + */ +static inline unsigned int aarch64_banked_spsr_index(unsigned int el) +{ + static const unsigned int map[4] = { + [1] = 0, /* EL1. */ + [2] = 6, /* EL2. */ + [3] = 7, /* EL3. */ + }; + assert(el >= 1 && el <= 3); + return map[el]; +} + int bank_number(int mode); void switch_mode(CPUARMState *, int); void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index f120b02..c05a839 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -386,7 +386,8 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) void HELPER(exception_return)(CPUARMState *env) { - uint32_t spsr = env->banked_spsr[0]; + unsigned int spsr_idx = is_a64(env) ? aarch64_banked_spsr_index(1) : 0; + uint32_t spsr = env->banked_spsr[spsr_idx]; int new_el, i; if (env->pstate & PSTATE_SP) {