diff mbox

[1/2] target-mips: pass CPUMIPSState to gen_mfc0/mtc0/dmfc0/dmtc0

Message ID 1400264014-78911-2-git-send-email-petar.jovanovic@rt-rk.com
State New
Headers show

Commit Message

Petar Jovanovic May 16, 2014, 6:13 p.m. UTC 
From: Petar Jovanovic <petar.jovanovic@imgtec.com>

Add CPUMIPSState in gen_mfc0/mtc0/dmfc0/dmtc0, as it will be used in the
next patch that implements UserLocal register and access to it.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
---
 target-mips/translate.c |   44 ++++++++++++++++++++++++--------------------
 1 file changed, 24 insertions(+), 20 deletions(-)

Comments

Richard Henderson May 17, 2014, 6:03 p.m. UTC | #1 
On 05/16/2014 11:13 AM, Petar Jovanovic wrote:
>  
> -static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> +static void gen_mfc0(CPUMIPSState *env, DisasContext *ctx,
> +    

You should not be passing around env within the translator, at all.

You should be able to get everything you need from ctx->hflags
or ctx->insn_flags.  If there's something missing from ctx, then
we'll talk about additional changes.


r~
diff mbox

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 05f82d2..d629b73 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4070,7 +4070,8 @@  static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
     tcg_gen_st_tl(arg, cpu_env, off);
 }
 
-static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_mfc0(CPUMIPSState *env, DisasContext *ctx,
+                     TCGv arg, int reg, int sel)
 {
     const char *rn = "invalid";
 
@@ -4657,7 +4658,8 @@  die:
     generate_exception(ctx, EXCP_RI);
 }
 
-static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_mtc0(CPUMIPSState *env, DisasContext *ctx,
+                     TCGv arg, int reg, int sel)
 {
     const char *rn = "invalid";
 
@@ -5264,7 +5266,8 @@  die:
 }
 
 #if defined(TARGET_MIPS64)
-static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_dmfc0(CPUMIPSState *env, DisasContext *ctx,
+                      TCGv arg, int reg, int sel)
 {
     const char *rn = "invalid";
 
@@ -5833,7 +5836,8 @@  die:
     generate_exception(ctx, EXCP_RI);
 }
 
-static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_dmtc0(CPUMIPSState *env, DisasContext *ctx,
+                      TCGv arg, int reg, int sel)
 {
     const char *rn = "invalid";
 
@@ -6483,7 +6487,7 @@  static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
                 gen_helper_mftc0_tcschefback(t0, cpu_env);
                 break;
             default:
-                gen_mfc0(ctx, t0, rt, sel);
+                gen_mfc0(env, ctx, t0, rt, sel);
                 break;
             }
             break;
@@ -6493,7 +6497,7 @@  static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
                 gen_helper_mftc0_entryhi(t0, cpu_env);
                 break;
             default:
-                gen_mfc0(ctx, t0, rt, sel);
+                gen_mfc0(env, ctx, t0, rt, sel);
                 break;
             }
         case 12:
@@ -6502,7 +6506,7 @@  static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
                 gen_helper_mftc0_status(t0, cpu_env);
                 break;
             default:
-                gen_mfc0(ctx, t0, rt, sel);
+                gen_mfc0(env, ctx, t0, rt, sel);
                 break;
             }
         case 13:
@@ -6551,12 +6555,12 @@  static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
                 gen_helper_mftc0_debug(t0, cpu_env);
                 break;
             default:
-                gen_mfc0(ctx, t0, rt, sel);
+                gen_mfc0(env, ctx, t0, rt, sel);
                 break;
             }
             break;
         default:
-            gen_mfc0(ctx, t0, rt, sel);
+            gen_mfc0(env, ctx, t0, rt, sel);
         }
     } else switch (sel) {
     /* GPR registers. */
@@ -6701,7 +6705,7 @@  static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
                 gen_helper_mttc0_tcschefback(cpu_env, t0);
                 break;
             default:
-                gen_mtc0(ctx, t0, rd, sel);
+                gen_mtc0(env, ctx, t0, rd, sel);
                 break;
             }
             break;
@@ -6711,7 +6715,7 @@  static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
                 gen_helper_mttc0_entryhi(cpu_env, t0);
                 break;
             default:
-                gen_mtc0(ctx, t0, rd, sel);
+                gen_mtc0(env, ctx, t0, rd, sel);
                 break;
             }
         case 12:
@@ -6720,7 +6724,7 @@  static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
                 gen_helper_mttc0_status(cpu_env, t0);
                 break;
             default:
-                gen_mtc0(ctx, t0, rd, sel);
+                gen_mtc0(env, ctx, t0, rd, sel);
                 break;
             }
         case 13:
@@ -6749,12 +6753,12 @@  static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
                 gen_helper_mttc0_debug(cpu_env, t0);
                 break;
             default:
-                gen_mtc0(ctx, t0, rd, sel);
+                gen_mtc0(env, ctx, t0, rd, sel);
                 break;
             }
             break;
         default:
-            gen_mtc0(ctx, t0, rd, sel);
+            gen_mtc0(env, ctx, t0, rd, sel);
         }
     } else switch (sel) {
     /* GPR registers. */
@@ -6861,7 +6865,7 @@  static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
             /* Treat as NOP. */
             return;
         }
-        gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
+        gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
         opn = "mfc0";
         break;
     case OPC_MTC0:
@@ -6869,7 +6873,7 @@  static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
             TCGv t0 = tcg_temp_new();
 
             gen_load_gpr(t0, rt);
-            gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7);
+            gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
             tcg_temp_free(t0);
         }
         opn = "mtc0";
@@ -6881,7 +6885,7 @@  static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
             /* Treat as NOP. */
             return;
         }
-        gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
+        gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
         opn = "dmfc0";
         break;
     case OPC_DMTC0:
@@ -6890,7 +6894,7 @@  static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
             TCGv t0 = tcg_temp_new();
 
             gen_load_gpr(t0, rt);
-            gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7);
+            gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
             tcg_temp_free(t0);
         }
         opn = "dmtc0";
@@ -11068,7 +11072,7 @@  static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
             /* Treat as NOP. */
             break;
         }
-        gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7);
+        gen_mfc0(env, ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7);
         break;
     case MTC0:
     case MTC0 + 32:
@@ -11077,7 +11081,7 @@  static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
             TCGv t0 = tcg_temp_new();
 
             gen_load_gpr(t0, rt);
-            gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
+            gen_mtc0(env, ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
             tcg_temp_free(t0);
         }
         break;