From patchwork Fri May 16 16:57:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 349690 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CE0B2140079 for ; Sat, 17 May 2014 02:58:57 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type:content-transfer-encoding; q=dns; s= default; b=AjaAYzaR4T9Na00k5hPHgOdcRDtW1GTUwLSraDtImiz4KE+u7+h6W cm0ehMQAWWioDrmr3TXvoJrRAVpTD/i5cvddxenqn117lq3heoB2TSwYXZk9+yYa InAbh7CYDdvHbu/Zf0SEQNIRB0dsrRlrRddk7uyWaRZFiRQ8MGvZrI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type:content-transfer-encoding; s=default; bh=yDf2fgEDA55eU6hZQUUlYVHfwKk=; b=lRcea+R+9VKS4H06znFAeMfaTZPN xbLBlXB7cHvbH7a48cMNQJWr5YBgmpfSecd0/FDcOtHrNj8TYinQpSJrifiDpDIf TFb93s54o2gkflVnDv0Yj7zvgEX79cjgD8CXRu47bejTQhpo0R9W/O1WzF4Y4tWs U3oo65sAqY2t0Jk= Received: (qmail 26098 invoked by alias); 16 May 2014 16:58:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 26075 invoked by uid 89); 16 May 2014 16:58:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 16 May 2014 16:58:49 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1WlLT1-0002SG-VJ from Maciej_Rozycki@mentor.com ; Fri, 16 May 2014 09:58:44 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 16 May 2014 09:58:43 -0700 Received: from localhost (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server (TLS) id 14.2.247.3; Fri, 16 May 2014 17:58:41 +0100 Date: Fri, 16 May 2014 17:57:51 +0100 From: "Maciej W. Rozycki" To: Joey Ye , "Joseph S. Myers" CC: , Subject: Re: [PATCH] Fix ARM NAN fraction bits In-Reply-To: <000b01cf3367$439c5280$cad4f780$@arm.com> Message-ID: References: <000b01cf3367$439c5280$cad4f780$@arm.com> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 On Thu, 27 Feb 2014, Joey Ye wrote: > Current ARM soft-float implementation is violating the RTABI > (http://infocenter.arm.com/help/topic/com.arm.doc.ihi0043d/IHI0043D_rtabi.pd > f) Section 4.1.1.1: > > When not otherwise specified by IEEE 754, the result on an invalid operation > should be the quiet NaN bit pattern with only the most significant bit of > the significand set, and all other significand bits zero. > > This patch fixes it by setting _FP_NANFRAC_* to zero. > > Ran make check test with –mfloat-abi=soft. No regression. > > OK to checkin? > > 2014-02-27  Joey Ye  > * sysdeps/arm/soft-fp/sfp-machine.h >   (_FP_NANFRAC_S, _FP_NANFRAC_D, _FP_NANFRAC_Q): >   Set to zero. > > > diff --git a/sysdeps/arm/soft-fp/sfp-machine.h > b/sysdeps/arm/soft-fp/sfp-machine.h > index 52a08b5..32697fe 100644 > --- a/sysdeps/arm/soft-fp/sfp-machine.h > +++ b/sysdeps/arm/soft-fp/sfp-machine.h > @@ -21,9 +21,9 @@ > #define _FP_DIV_MEAT_D(R,X,Y)          _FP_DIV_MEAT_2_udiv(D,R,X,Y) > #define _FP_DIV_MEAT_Q(R,X,Y)          _FP_DIV_MEAT_4_udiv(Q,R,X,Y) > > -#define _FP_NANFRAC_S                          ((_FP_QNANBIT_S << 1) - 1) > -#define _FP_NANFRAC_D                         ((_FP_QNANBIT_D << 1) - 1), > -1 > -#define _FP_NANFRAC_Q                         ((_FP_QNANBIT_Q << 1) - 1), > -1, -1, -1 > +#define _FP_NANFRAC_S                         0 > +#define _FP_NANFRAC_D                        0, 0 > +#define _FP_NANFRAC_Q                        0, 0, 0, 0 > #define _FP_NANSIGN_S                           0 > #define _FP_NANSIGN_D                          0 > #define _FP_NANSIGN_Q                          0 This did regrettably, when propagated to libgcc, regress gcc.dg/torture/builtin-math-7.c on soft-fp arm-eabi targets, currently ARMv6-M (`-march=armv6-m -mthumb') only. This is because these NANFRAC macros have now no bits set and as a result when used to construct a NaN in the semi-raw mode, they build an infinity instead. Consequently operations such as (Inf - Inf) now produce Inf rather than NaN. The change worked for the original test case, because division is made in the canonical mode, where the quiet bit is set separately, from the fp class. Here's a fix making code match the commit description quoted above, that is set the most significant bit of the significand. This is also what targets similar in this respect do. OK to apply? OK for libgcc (against libgcc/config/arm/sfp-machine.h), in particular for GCC 4.8 and 4.9? 2014-05-16 Maciej W. Rozycki PR libgcc/60166 * sysdeps/arm/soft-fp/sfp-machine.h (_FP_NANFRAC_S, _FP_NANFRAC_D) (_FP_NANSIGN_Q): Set the quiet bit. Maciej glibc-soft-fp-arm-nanfrac.diff Index: glibc-fsf-trunk-quilt/sysdeps/arm/soft-fp/sfp-machine.h =================================================================== --- glibc-fsf-trunk-quilt.orig/sysdeps/arm/soft-fp/sfp-machine.h 2014-05-16 03:25:52.000000000 +0100 +++ glibc-fsf-trunk-quilt/sysdeps/arm/soft-fp/sfp-machine.h 2014-05-16 03:31:34.451805339 +0100 @@ -21,9 +21,9 @@ #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) -#define _FP_NANFRAC_S 0 -#define _FP_NANFRAC_D 0, 0 -#define _FP_NANFRAC_Q 0, 0, 0, 0 +#define _FP_NANFRAC_S _FP_QNANBIT_S +#define _FP_NANFRAC_D _FP_QNANBIT_D, 0 +#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0 #define _FP_NANSIGN_S 0 #define _FP_NANSIGN_D 0 #define _FP_NANSIGN_Q 0