From patchwork Mon Oct 5 08:20:01 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 34946 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A17CCB7BC0 for ; Mon, 5 Oct 2009 19:31:21 +1100 (EST) Received: from localhost ([127.0.0.1]:60951 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MuiyU-0007OW-5a for incoming@patchwork.ozlabs.org; Mon, 05 Oct 2009 04:31:18 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Muixu-0007OH-TS for qemu-devel@nongnu.org; Mon, 05 Oct 2009 04:30:42 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Muixp-0007LX-TH for qemu-devel@nongnu.org; Mon, 05 Oct 2009 04:30:42 -0400 Received: from [199.232.76.173] (port=33969 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Muixp-0007LJ-PG for qemu-devel@nongnu.org; Mon, 05 Oct 2009 04:30:37 -0400 Received: from va3ehsobe004.messaging.microsoft.com ([216.32.180.14]:49032 helo=VA3EHSOBE004.bigfish.com) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_ARCFOUR_MD5:16) (Exim 4.60) (envelope-from ) id 1Muixp-0003Ma-Ak for qemu-devel@nongnu.org; Mon, 05 Oct 2009 04:30:37 -0400 Received: from mail24-va3-R.bigfish.com (10.7.14.244) by VA3EHSOBE004.bigfish.com (10.7.40.24) with Microsoft SMTP Server id 8.1.340.0; Mon, 5 Oct 2009 08:30:35 +0000 Received: from mail24-va3 (localhost.localdomain [127.0.0.1]) by mail24-va3-R.bigfish.com (Postfix) with ESMTP id C067818C81D2; Mon, 5 Oct 2009 08:30:34 +0000 (UTC) X-SpamScore: -7 X-BigFish: VPS-7(zz1447Rzz1202hzzz32i6bh43j61h) X-Spam-TCS-SCL: 0:0 Received: by mail24-va3 (MessageSwitch) id 1254731431487811_29120; Mon, 5 Oct 2009 08:30:31 +0000 (UCT) Received: from VA3EHSMHS023.bigfish.com (unknown [10.7.14.236]) by mail24-va3.bigfish.com (Postfix) with ESMTP id 3796712200A3; Mon, 5 Oct 2009 08:30:06 +0000 (UTC) Received: from svlb1extmailp02.amd.com (139.95.251.11) by VA3EHSMHS023.bigfish.com (10.7.99.33) with Microsoft SMTP Server (TLS) id 14.0.482.32; Mon, 5 Oct 2009 08:30:05 +0000 Received: from svlb1twp02.amd.com ([139.95.250.35]) by svlb1extmailp02.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n958Tvpf006892; Mon, 5 Oct 2009 01:30:00 -0700 X-WSS-ID: 0KR18XZ-04-4M5-02 X-M-MSG: Received: from SSVLEXBH2.amd.com (ssvlexbh2.amd.com [139.95.53.183]) by svlb1twp02.amd.com (Tumbleweed MailGate 3.7.0) with ESMTP id 2AC841B10296; Mon, 5 Oct 2009 01:29:58 -0700 (PDT) Received: from SSVLEXMB1.amd.com ([139.95.53.181]) by SSVLEXBH2.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 5 Oct 2009 01:30:00 -0700 Received: from SF30EXMB1.amd.com ([172.20.6.49]) by SSVLEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 5 Oct 2009 01:30:00 -0700 Received: from seurexmb1.amd.com ([165.204.9.130]) by SF30EXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 5 Oct 2009 10:29:57 +0200 Received: from gwo.osrc.amd.com ([165.204.16.204]) by seurexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 5 Oct 2009 10:29:56 +0200 Received: from localhost.localdomain (hagen.osrc.amd.com [165.204.15.42]) by gwo.osrc.amd.com (Postfix) with ESMTP id 5D29B49C130; Mon, 5 Oct 2009 09:29:56 +0100 (BST) From: Andre Przywara To: aurelien@aurel32.net Date: Mon, 5 Oct 2009 10:20:01 +0200 Message-ID: <1254730801-5045-1-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.6.1.3 In-Reply-To: <20091004120249.GO6691@hall.aurel32.net> References: <20091004120249.GO6691@hall.aurel32.net> X-OriginalArrivalTime: 05 Oct 2009 08:29:56.0608 (UTC) FILETIME=[0513E000:01CA4596] MIME-Version: 1.0 X-Reverse-DNS: unknown X-detected-operating-system: by monty-python.gnu.org: Windows 2000 SP4, XP SP1+ Cc: Andre Przywara , qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 1/4 v2] TCG x86: implement lzcnt emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org lzcnt is a AMD Phenom/Barcelona added instruction returning the number of leading zero bits in a word. As this is similar to the "bsr" instruction, reuse the existing code. There need to be some more changes, though, as lzcnt always returns a valid value (in opposite to bsr, which has a special case when the operand is 0). lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5). Signed-off-by: Andre Przywara --- target-i386/helper.h | 1 + target-i386/op_helper.c | 14 ++++++++++++-- target-i386/translate.c | 37 +++++++++++++++++++++++++------------ 3 files changed, 38 insertions(+), 14 deletions(-) Aurelien, this version addresses your comments. Thanks for the review (and the other commits)! Regards, Andre. diff --git a/target-i386/helper.h b/target-i386/helper.h index ca953f4..6b518ad 100644 --- a/target-i386/helper.h +++ b/target-i386/helper.h @@ -193,6 +193,7 @@ DEF_HELPER_2(fxsave, void, tl, int) DEF_HELPER_2(fxrstor, void, tl, int) DEF_HELPER_1(bsf, tl, tl) DEF_HELPER_1(bsr, tl, tl) +DEF_HELPER_2(lzcnt, tl, tl, int) /* MMX/SSE */ diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index 26fe612..5eea322 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -5479,11 +5479,14 @@ target_ulong helper_bsf(target_ulong t0) return count; } -target_ulong helper_bsr(target_ulong t0) +target_ulong helper_lzcnt(target_ulong t0, int wordsize) { int count; target_ulong res, mask; - + + if (wordsize > 0 && t0 == 0) { + return wordsize; + } res = t0; count = TARGET_LONG_BITS - 1; mask = (target_ulong)1 << (TARGET_LONG_BITS - 1); @@ -5491,9 +5494,16 @@ target_ulong helper_bsr(target_ulong t0) count--; res <<= 1; } + if (wordsize > 0) { + return wordsize - 1 - count; + } return count; } +target_ulong helper_bsr(target_ulong t0) +{ + return helper_lzcnt(t0, 0); +} static int compute_all_eflags(void) { diff --git a/target-i386/translate.c b/target-i386/translate.c index e3cb49f..5cbdce1 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -6575,22 +6575,35 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) reg = ((modrm >> 3) & 7) | rex_r; gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); gen_extu(ot, cpu_T[0]); - label1 = gen_new_label(); - tcg_gen_movi_tl(cpu_cc_dst, 0); t0 = tcg_temp_local_new(); tcg_gen_mov_tl(t0, cpu_T[0]); - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1); - if (b & 1) { - gen_helper_bsr(cpu_T[0], t0); + if ((b & 1) && (prefixes & PREFIX_REPZ) && + (s->cpuid_ext3_features & CPUID_EXT3_ABM)) { + switch(ot) { + case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0, + tcg_const_i32(16)); break; + case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0, + tcg_const_i32(32)); break; + case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0, + tcg_const_i32(64)); break; + } + gen_op_mov_reg_T0(ot, reg); } else { - gen_helper_bsf(cpu_T[0], t0); + label1 = gen_new_label(); + tcg_gen_movi_tl(cpu_cc_dst, 0); + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1); + if (b & 1) { + gen_helper_bsr(cpu_T[0], t0); + } else { + gen_helper_bsf(cpu_T[0], t0); + } + gen_op_mov_reg_T0(ot, reg); + tcg_gen_movi_tl(cpu_cc_dst, 1); + gen_set_label(label1); + tcg_gen_discard_tl(cpu_cc_src); + s->cc_op = CC_OP_LOGICB + ot; + tcg_temp_free(t0); } - gen_op_mov_reg_T0(ot, reg); - tcg_gen_movi_tl(cpu_cc_dst, 1); - gen_set_label(label1); - tcg_gen_discard_tl(cpu_cc_src); - s->cc_op = CC_OP_LOGICB + ot; - tcg_temp_free(t0); } break; /************************/