Patchwork [3.11.y.z,extended,stable] Patch "fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6" has been added to staging queue

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Submitter Luis Henriques
Date May 14, 2014, 2:57 p.m.
Message ID <>
Download mbox | patch
Permalink /patch/348842/
State New
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Luis Henriques - May 14, 2014, 2:57 p.m.
This is a note to let you know that I have just added a patch titled

    fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6

to the linux-3.11.y-queue branch of the 3.11.y.z extended stable tree 
which can be found at:;a=shortlog;h=refs/heads/linux-3.11.y-queue

If you, or anyone else, feels it should not be added to this tree, please 
reply to this email.

For more information about the 3.11.y.z tree, see



From b4c23fc9b8dcb639de74e2aee55e6266ee464a11 Mon Sep 17 00:00:00 2001
From: Nikita Yushchenko <>
Date: Mon, 28 Apr 2014 19:23:44 +0400
Subject: fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6

commit d183c81929beeba842b74422f754446ef2b8b49c upstream.

Per reference manuals of Freescale P1020 and P2020 SoCs, USB controller
present in these SoCs has bit 17 of USBx_CONTROL register marked as
Reserved - there is no PHY_CLK_VALID bit there.

Testing for this bit in ehci_fsl_setup_phy() behaves differently on two
P1020RDB boards available here - on one board test passes and fsl-usb
init succeeds, but on other board test fails, causing fsl-usb init to

This patch changes ehci_fsl_setup_phy() not to test PHY_CLK_VALID on
controller version 1.6 that (per manual) does not have this bit.

Signed-off-by: Nikita Yushchenko <>
Signed-off-by: Greg Kroah-Hartman <>
Signed-off-by: Luis Henriques <>
 drivers/usb/host/ehci-fsl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 87c1a2e..164e381 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -261,7 +261,8 @@  static int ehci_fsl_setup_phy(struct usb_hcd *hcd,

-	if (pdata->have_sysif_regs && pdata->controller_ver &&
+	if (pdata->have_sysif_regs &&
+	    pdata->controller_ver > FSL_USB_VER_1_6 &&
 	    (phy_mode == FSL_USB2_PHY_ULPI)) {
 		/* check PHY_CLK_VALID to get phy clk valid */
 		if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &