[v2,02/23] target-arm: move SCR into Security Extensions register list

From: Sergey Fedorov <s.fedorov@samsung.com>

Define a new ARM CP register info list for the Security Extension feature.
Register that list only for ARM cores with Security Extension support.
Moving SCR into Security Extension register group.

Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
---
 target-arm/helper.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

On 13 May 2014 11:15, Fabian Aggeler <aggelerf@ethz.ch> wrote:

> From: Sergey Fedorov <s.fedorov@samsung.com>
>
> Define a new ARM CP register info list for the Security Extension feature.
> Register that list only for ARM cores with Security Extension support.
> Moving SCR into Security Extension register group.
>
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> ---
>  target-arm/helper.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 3be917c..7898f40 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -768,9 +768,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .access = PL1_RW, .writefn = vbar_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
>        .resetvalue = 0 },
> -    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
> -      .resetvalue = 0, },
>      { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
>        .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
> @@ -2087,6 +2084,15 @@ static void sctlr_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
>      tlb_flush(CPU(cpu), 1);
>  }
>
> +static const ARMCPRegInfo tz_cp_reginfo[] = {
>

Sticking with the feature name switch from TRUSTZONE to SECURITY, for
consistency we should call this security_cp_reginfo.


> +#ifndef CONFIG_USER_ONLY
> +    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> +      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
> +      .resetvalue = 0, },
> +#endif
> +    REGINFO_SENTINEL
> +};
> +
>  static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo
> *ri)
>  {
>      /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
> @@ -2364,6 +2370,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>      if (arm_feature(env, ARM_FEATURE_LPAE)) {
>          define_arm_cp_regs(cpu, lpae_cp_reginfo);
>      }
> +    if (arm_feature(env, ARM_FEATURE_SECURITY_EXTENSIONS)) {
> +        define_arm_cp_regs(cpu, tz_cp_reginfo);
> +    }
>      /* Slightly awkwardly, the OMAP and StrongARM cores need all of
>       * cp15 crn=0 to be writes-ignored, whereas for other cores they
> should
>       * be read-only (ie write causes UNDEF exception).
> --
> 1.8.3.2
>
>
>

On 13 May 2014 17:15, Fabian Aggeler <aggelerf@ethz.ch> wrote:
> From: Sergey Fedorov <s.fedorov@samsung.com>
>
> Define a new ARM CP register info list for the Security Extension feature.
> Register that list only for ARM cores with Security Extension support.
> Moving SCR into Security Extension register group.
>
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> ---
>  target-arm/helper.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 3be917c..7898f40 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -768,9 +768,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .access = PL1_RW, .writefn = vbar_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
>        .resetvalue = 0 },
> -    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
> -      .resetvalue = 0, },
>      { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
>        .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
> @@ -2087,6 +2084,15 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>      tlb_flush(CPU(cpu), 1);
>  }
>
> +static const ARMCPRegInfo tz_cp_reginfo[] = {
> +#ifndef CONFIG_USER_ONLY
> +    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> +      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
> +      .resetvalue = 0, },
> +#endif

Why has this acquired CONFIG_USER_ONLY guards? It doesn't
seem to need them...

thanks
-- PMM