From patchwork Fri Oct 2 10:31:53 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 34823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9C529B7BC7 for ; Fri, 2 Oct 2009 20:49:43 +1000 (EST) Received: from localhost ([127.0.0.1]:46476 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mtfhl-0007C3-09 for incoming@patchwork.ozlabs.org; Fri, 02 Oct 2009 06:49:41 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MtfSc-0001De-Er for qemu-devel@nongnu.org; Fri, 02 Oct 2009 06:34:02 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MtfSU-0001AN-RZ for qemu-devel@nongnu.org; Fri, 02 Oct 2009 06:33:58 -0400 Received: from [199.232.76.173] (port=51012 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MtfST-00019V-Nv for qemu-devel@nongnu.org; Fri, 02 Oct 2009 06:33:53 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:39076) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MtfSR-0004O5-Ou for qemu-devel@nongnu.org; Fri, 02 Oct 2009 06:33:52 -0400 Received: from nm.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with ESMTP id 8AD3B49CF9; Fri, 2 Oct 2009 19:33:36 +0900 (JST) Received: from yamahata by nm.local.valinux.co.jp with local (Exim 4.69) (envelope-from ) id 1MtfQc-0006kI-PO; Fri, 02 Oct 2009 19:31:58 +0900 From: Isaku Yamahata To: qemu-devel@nongnu.org, anthony@codemonkey.ws Date: Fri, 2 Oct 2009 19:31:53 +0900 Message-Id: <1254479517-25845-22-git-send-email-yamahata@valinux.co.jp> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1254479517-25845-1-git-send-email-yamahata@valinux.co.jp> References: <1254479517-25845-1-git-send-email-yamahata@valinux.co.jp> X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: yamahata@valinux.co.jp Subject: [Qemu-devel] [PATCH 21/25] pci: make bar update function aware of pci bridge. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org header type of 01 has differenct BAR to type 00. It has only BAR0,1 and expantion rom whose offset address is different from type 00 one. Signed-off-by: Isaku Yamahata --- hw/pci.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++---------- hw/pci.h | 1 + 2 files changed, 56 insertions(+), 11 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 7910800..1d638c4 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -498,6 +498,35 @@ int pci_unregister_device(PCIDevice *pci_dev) return 0; } +#define PCI_BAR_INVALID UINT32_MAX +static uint32_t pci_bar_config_offset(PCIDevice *d, int region_num) +{ + switch (d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION) { + case PCI_HEADER_TYPE_NORMAL: + /* BAR 0-5 and Expantion ROM*/ + if (region_num < PCI_ROM_SLOT) { + return PCI_BASE_ADDRESS_0 + region_num * 4; + } else if (region_num == PCI_ROM_SLOT) { + return PCI_ROM_ADDRESS; + } + break; + case PCI_HEADER_TYPE_BRIDGE: + /* BAR 0-1 and Expantion ROM */ + if (region_num < 2) { + return PCI_BASE_ADDRESS_0 + region_num * 4; + } else if (region_num == PCI_ROM_SLOT) { + return PCI_ROM_ADDRESS1; + } + break; + case PCI_HEADER_TYPE_CARDBUS: + default: + break; + } + fprintf(stderr, "ERROR: %s: unknow PCI config header type %d or bar %d\n", + __func__, d->config[PCI_HEADER_TYPE], region_num); + return PCI_BAR_INVALID; +} + void pci_register_bar(PCIDevice *pci_dev, int region_num, pcibus_t size, int type, PCIMapIORegionFunc *map_func) @@ -521,13 +550,11 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, r->type = type; r->map_func = map_func; + addr = pci_bar_config_offset(pci_dev, region_num); wmask = ~(size - 1); if (region_num == PCI_ROM_SLOT) { - addr = 0x30; /* ROM enable bit is writeable */ wmask |= PCI_ROM_ADDRESS_ENABLE; - } else { - addr = 0x10 + region_num * 4; } pci_set_long(pci_dev->config + addr, type); if (pci_bar_is_64bit(r)) { @@ -549,11 +576,9 @@ static void pci_update_mappings(PCIDevice *d) cmd = pci_get_word(d->config + PCI_COMMAND); for(i = 0; i < PCI_NUM_REGIONS; i++) { r = &d->io_regions[i]; - if (i == PCI_ROM_SLOT) { - config_ofs = 0x30; - } else { - config_ofs = 0x10 + i * 4; - } + + config_ofs = pci_bar_config_offset(d, i); + if (r->size != 0) { if (r->type & PCI_ADDRESS_SPACE_IO) { if (cmd & PCI_COMMAND_IO) { @@ -1134,10 +1159,29 @@ static void pci_bridge_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { PCIBridge *s = (PCIBridge *)d; + PCIBus *bus = s->bus; + uint8_t *orig = pci_write_config_init(d, address, len); + + pci_default_write_config_common(d, address, val, len); - pci_default_write_config(d, address, val, len); - s->bus->bus_num = d->config[PCI_SECONDARY_BUS]; - s->bus->sub_bus = d->config[PCI_SUBORDINATE_BUS]; + if (pci_config_changed(orig, d->config, address, len, + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2 + 4) || + pci_config_changed_with_size(orig, d->config, address, len, + PCI_ROM_ADDRESS1, 4) || + pci_config_changed_with_size(orig, d->config, address, len, + PCI_COMMAND, 1)) { + pci_update_mappings(d); + } + if (pci_config_changed_with_size(orig, d->config, address, len, + PCI_SECONDARY_BUS, 1)) { + bus->bus_num = d->config[PCI_SECONDARY_BUS]; + } + if (pci_config_changed_with_size(orig, d->config, address, len, + PCI_SECONDARY_BUS, 1)) { + bus->sub_bus = d->config[PCI_SUBORDINATE_BUS]; + } + + pci_write_config_done(orig); } PCIBus *pci_find_bus(PCIBus *bus, int bus_num) diff --git a/hw/pci.h b/hw/pci.h index f19b7a8..645dacd 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -174,6 +174,7 @@ static inline int pci_bar_is_64bit(const PCIIORegion *r) /* Header type 1 (PCI-to-PCI bridges) */ #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ +#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ /* Size of the standard PCI config header */ #define PCI_CONFIG_HEADER_SIZE 0x40