From patchwork Mon May 12 16:06:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel Fernandez X-Patchwork-Id: 348066 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3B3E9140083 for ; Tue, 13 May 2014 02:12:38 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755874AbaELQML (ORCPT ); Mon, 12 May 2014 12:12:11 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:49454 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755921AbaELQIx (ORCPT ); Mon, 12 May 2014 12:08:53 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id s4CFX5g5023465; Mon, 12 May 2014 18:07:44 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 1ktstfabxk-1 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NOT); Mon, 12 May 2014 18:07:44 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 63A3B51; Mon, 12 May 2014 16:06:59 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0DDEC59F46; Mon, 12 May 2014 16:06:59 +0000 (GMT) Received: from lmenx315.lme.st.com (lmenx315.lme.st.com [10.201.19.41]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BZH06825 (AUTH frq07381); Mon, 12 May 2014 18:06:57 +0200 From: Gabriel FERNANDEZ To: mturquette@linaro.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, rdunlap@infradead.org Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, Lee Jones , Gabriel Fernandez Subject: [PATCH 01/12] clk: st: Update ST clock binding documentation Date: Mon, 12 May 2014 18:06:29 +0200 Message-Id: <1399910800-12847-2-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1399910800-12847-1-git-send-email-gabriel.fernandez@linaro.org> References: <1399910800-12847-1-git-send-email-gabriel.fernandez@linaro.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.11.96, 1.0.14, 0.0.0000 definitions=2014-05-12_02:2014-05-12, 2014-05-12, 1970-01-01 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds new compatibilities to support STiH407 SoC. Signed-off-by: Gabriel Fernandez --- .../devicetree/bindings/clock/st/st,clkgen-mux.txt | 2 +- .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 5 ++++- .../devicetree/bindings/clock/st/st,clkgen.txt | 20 ++++++++++++++++---- .../devicetree/bindings/clock/st/st,quadfs.txt | 3 +++ 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt index 943e080..2d92fc8 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt @@ -17,7 +17,7 @@ Required properties: "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux" "st,stih415-clkgen-a9-mux", "st,clkgen-mux" "st,stih416-clkgen-a9-mux", "st,clkgen-mux" - + "st,stih407-clkgen-a9-mux", "st,clkgen-mux" - #clock-cells : from common clock binding; shall be set to 0. diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index 81eb385..b852925 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -19,11 +19,14 @@ Required properties: "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32" "st,stih416-plls-c32-a9", "st,clkgen-plls-c32" "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32" + "st,stih407-plls-c32-a0", "st,clkgen-plls-c32" + "st,stih407-plls-c32-a9", "st,clkgen-plls-c32" + "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32" + "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32" "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32" "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32" - - #clock-cells : From common clock binding; shall be set to 1. - clocks : From common clock binding diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt index 49ec5ae..55506c2 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt @@ -24,16 +24,28 @@ address is common of all subnode. quadfs_node { ... }; + + mux_node { + ... + }; + + vcc_node { + ... + }; ... }; This binding uses the common clock binding[1]. -Each subnode should use the binding discribe in [2]..[4] +Each subnode should use the binding discribe in [2]..[7] [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/st,quadfs.txt -[3] Documentation/devicetree/bindings/clock/st,quadfs.txt -[4] Documentation/devicetree/bindings/clock/st,quadfs.txt +[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt +[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt +[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt +[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt +[6] Documentation/devicetree/bindings/clock/st,vcc.txt +[7] Documentation/devicetree/bindings/clock/st,quadfs.txt + Required properties: - reg : A Base address and length of the register set. diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index ec86d62..c0a4045 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -15,6 +15,9 @@ Required properties: "st,stih416-quadfs432", "st,quadfs" "st,stih416-quadfs660-E", "st,quadfs" "st,stih416-quadfs660-F", "st,quadfs" + "st,stih407-quadfs660-C", "st,quadfs" + "st,stih407-quadfs660-D", "st,quadfs" + - #clock-cells : from common clock binding; shall be set to 1.