From patchwork Thu May 8 23:03:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loc Ho X-Patchwork-Id: 347267 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 7EA7D1400CB for ; Fri, 9 May 2014 09:03:42 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755972AbaEHXDl (ORCPT ); Thu, 8 May 2014 19:03:41 -0400 Received: from exprod5og102.obsmtp.com ([64.18.0.143]:50508 "HELO exprod5og102.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1755966AbaEHXDl (ORCPT ); Thu, 8 May 2014 19:03:41 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]) (using TLSv1) by exprod5ob102.postini.com ([64.18.4.12]) with SMTP ID DSNKU2wNTD2GYNuLwzWS+XyQ3Dfwhgvr7BWe@postini.com; Thu, 08 May 2014 16:03:41 PDT Received: by mail-pa0-f42.google.com with SMTP id rd3so3483979pab.29 for ; Thu, 08 May 2014 16:03:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xrjVGVU5gwxVp6qt5HaqjDVYcNe3i+ZIV3E+0q+BgdE=; b=Dq4yRleaNPOkJq/aGQqOaCiqGaAImtf4KCmQjUYNu0jufn9bsfz4eMpY/1lzZwpeNm l32BD6zt3NvukwOnn3TgVhr23ST7PUckilzGIZxrZ8T0otqI21itmAOzQDLQDnG8dJD2 GooMe9kx/JPCGVEhGHAjdBPxv0d8DxpUlS06ZmNLAnD4pEdH8xtjyyH6U8uhrDXus0y7 oTAej4cfozHoZHvC8yxu2LKsMNNjoG3WWJq9dP47CqS6SVJuczzddxN20c3/G0mKVlpV CuMlGcSHB5VHQtPyhKLMelGJchK9y94VLHPt7UOmgQlhL5pu/0wTnex1YqN9ejKLO+Ia ZAvQ== X-Gm-Message-State: ALoCoQlpgv/LbvpvzTUlaXTnK6y+rQavA5pWeX7s7U0kL3bnFRw/gaNLmoSj5xv3h/kLyETXCCGi5gx4JoNzn4bDuGbXOrZ5UYd2/3jZxxBrt0tSvbwmemEuqoFSxOQ5rfizM9Ih3adN X-Received: by 10.66.171.206 with SMTP id aw14mr13186822pac.48.1399590220314; Thu, 08 May 2014 16:03:40 -0700 (PDT) X-Received: by 10.66.171.206 with SMTP id aw14mr13186814pac.48.1399590220265; Thu, 08 May 2014 16:03:40 -0700 (PDT) Received: from localhost ([198.137.200.11]) by mx.google.com with ESMTPSA id xo9sm10044946pab.18.2014.05.08.16.03.37 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 08 May 2014 16:03:38 -0700 (PDT) From: Loc Ho To: dougthompson@xmission.com, bp@alien8.de, m.chehab@samsung.com Cc: linux-edac@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jcm@redhat.com, patches@apm.com, Loc Ho , Feng Kan Subject: [PATCH 2/4] Documentation: Add documentation for the APM X-Gene SoC EDAC DTS binding Date: Thu, 8 May 2014 17:03:17 -0600 Message-Id: <1399590199-12256-3-git-send-email-lho@apm.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1399590199-12256-2-git-send-email-lho@apm.com> References: <1399590199-12256-1-git-send-email-lho@apm.com> <1399590199-12256-2-git-send-email-lho@apm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds documentation for the APM X-Gene SoC EDAC DTS binding. Signed-off-by: Feng Kan Signed-off-by: Loc Ho --- .../devicetree/bindings/edac/apm-xgene-edac.txt | 70 ++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt diff --git a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt new file mode 100644 index 0000000..c4ccc98 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt @@ -0,0 +1,70 @@ +* APM X-Gene EDAC nodes + +EDAC nodes are defined to describe on-chip error detection and correction. +There are four types of EDAC: + + memory controller - Memory controller + PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache + L3 - CPU L3 cache + SoC - SoC IP such as SATA, Ethernet. and etc + +The following section describes the memory controller DT node binding. + +Required properties: +- compatible : Shall be "apm,xgene-edac-mc". +- reg : First resource shall be the PCP resource. + Second resource shall be the CSW resource. + Third resource shall be the MCB-A resource. + Fourth resource shall be the MCB-B resource. + Fifth resource shall be the MCU resource. +- interrupts : Interrupt-specifier for MCU error IRQ. + +The following section describes the L1/L2 DT node binding. + +- compatible : Shall be "apm,xgene-edac-pmd". +- reg : First resource shall be the PCP resource. + Second resource shall be the PMD resource. +- interrupts : Interrupt-specifier for PMD error IRQ. + +The following section describes the L3 DT node binding. + +- compatible : Shall be "apm,xgene-edac-l3". +- reg : First resource shall be the PCP resource. + Second resource shall be the L3 resource. +- interrupts : Interrupt-specifier for L3 error IRQ. + +Example: + edacmc0: edacmc0@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e200000 0x0 0x1000>, + <0x0 0x7e700000 0x0 0x1000>, + <0x0 0x7e720000 0x0 0x1000>, + <0x0 0x7e800000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>; + }; + + edacl3: edacl3@7e600000 { + compatible = "apm,xgene-edac-l3"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e600000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>; + }; + + edacpmd0: edacpmd0@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7c000000 0x0 0x200000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>; + }; + + edacsoc: edacsoc@7e930000 { + compatible = "apm,xgene-edac-soc"; + reg = <0x0 0x78800000 0x0 0x1000>, + <0x0 0x7e930000 0x0 0x1000>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>, + <0x0 0x27 0x4>; + };