@@ -57,6 +57,10 @@
#define PCI_VENDOR_ID_AMD 0x1022
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
+#define PCI_VENDOR_ID_NEC 0x1033
+#define PCI_DEVICE_ID_NEC_CBUS_BRIDGE 0x0001
+#define PCI_DEVICE_ID_NEC_PC98_GRAPHICS 0x0009
+
#define PCI_VENDOR_ID_MOTOROLA 0x1057
#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
@@ -226,7 +226,9 @@ static int i440fx_initfn(PCIDevice *dev)
return 0;
}
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
+static PCIBus *i440fx_init_common(PCII440FXState **pi440fx_state,
+ int *piix3_devfn, qemu_irq *pic,
+ const char *piix3_name)
{
DeviceState *dev;
PCIBus *b;
@@ -247,12 +249,17 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *
(*pi440fx_state)->irq_state = irq_state;
irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
- pci_create_simple(b, -1, "PIIX3"));
+ pci_create_simple(b, -1, piix3_name));
*piix3_devfn = irq_state->piix3->dev.devfn;
return b;
}
+PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
+{
+ return i440fx_init_common(pi440fx_state, piix3_devfn, pic, "PIIX3");
+}
+
/* PIIX3 PCI to ISA bridge */
static void piix3_set_irq(void *opaque, int irq_num, int level)
@@ -329,23 +336,51 @@ static const VMStateDescription vmstate_piix3 = {
}
};
+static void piix3_initfn_common(PIIX3State *d)
+{
+ isa_bus_new(&d->dev.qdev);
+ vmstate_register(0, &vmstate_piix3, d);
+
+ piix3_reset(d);
+ qemu_register_reset(piix3_reset, d);
+}
+
static int piix3_initfn(PCIDevice *dev)
{
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
- uint8_t *pci_conf;
+ uint8_t *pci_conf = d->dev.config;
- isa_bus_new(&d->dev.qdev);
- vmstate_register(0, &vmstate_piix3, d);
+ piix3_initfn_common(d);
- pci_conf = d->dev.config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
pci_conf[PCI_HEADER_TYPE] =
PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
- piix3_reset(d);
- qemu_register_reset(piix3_reset, d);
+ return 0;
+}
+
+/* NEC PC-98x1 */
+
+PCIBus *pc98_i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
+{
+ return i440fx_init_common(pi440fx_state, piix3_devfn, pic, "STAR-ALPHA");
+}
+
+static int pc98_piix3_initfn(PCIDevice *dev)
+{
+ PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
+ uint8_t *pci_conf = d->dev.config;
+
+ piix3_initfn_common(d);
+
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_NEC);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_NEC_CBUS_BRIDGE); // Star Alpha
+ pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
+ pci_conf[PCI_HEADER_TYPE] =
+ PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
+
return 0;
}
@@ -364,6 +399,12 @@ static PCIDeviceInfo i440fx_info[] = {
.qdev.no_user = 1,
.init = piix3_initfn,
},{
+ .qdev.name = "STAR-ALPHA",
+ .qdev.desc = "CBUS bridge",
+ .qdev.size = sizeof(PIIX3State),
+ .qdev.no_user = 1,
+ .init = pc98_piix3_initfn,
+ },{
/* end of list */
}
};