From patchwork Tue May 6 08:10:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 346072 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id BE7641402CF for ; Tue, 6 May 2014 18:12:33 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934329AbaEFIMc (ORCPT ); Tue, 6 May 2014 04:12:32 -0400 Received: from mail-pd0-f182.google.com ([209.85.192.182]:43025 "EHLO mail-pd0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934321AbaEFIMb (ORCPT ); Tue, 6 May 2014 04:12:31 -0400 Received: by mail-pd0-f182.google.com with SMTP id v10so1505872pde.13 for ; Tue, 06 May 2014 01:12:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wgBFoccXut0wAknbsAf3nuFDqPF8oaI6/gJ88SkAB0U=; b=ARdPxzPmHg/XlLb3rShOJqGEmwTO58ZqnE1ZUxYnqHBTASMSXvMH4QE88rHsA1VRM+ c281ea52AuFwvX/zRJdMYp9ZRIyK8M59ufMFuLUphTBboxM+FIVdvvgjleOI2HPpvpkG R17TNmVjF2mLGR6+eWCLXU+YhcYgsece0IdSmmzJXj6xaI4uqhRfvzfdwsxLtOJvNYkl hSRV6Bifk95tfrroACTlZAS3NIE9LIdikQahhDszyjwPmXNFGoAnVnqkICpRGNQB/JFS 90+ZQntDYRrB1w5/rfNngUqfoj87/1nFzsI0nqyUXPw6tWb+2yFJwZjSxgJBu2FLg8Cd cb1A== X-Gm-Message-State: ALoCoQl0yFMdPEOJb+DR3Oybm+YA5uRdZIhucZ4Gov2yUuL3go+OgtakppHLDN1g+1TWgceAWhQ/ X-Received: by 10.67.2.34 with SMTP id bl2mr3624938pad.58.1399363950569; Tue, 06 May 2014 01:12:30 -0700 (PDT) Received: from linaro.sisodomain.com ([14.140.216.146]) by mx.google.com with ESMTPSA id vx10sm92059284pac.17.2014.05.06.01.12.14 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 06 May 2014 01:12:29 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, robh+dt@kernel.org, t.figa@samsung.com, sachin.kamat@linaro.org, kgene.kim@samsung.com, arnd@arndb.de, heiko@sntech.de Subject: [PATCH v2 2/2] Documentation: DT: Exynos: Bind SRAM though DT Date: Tue, 6 May 2014 13:40:24 +0530 Message-Id: <1399363824-23543-2-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399363824-23543-1-git-send-email-sachin.kamat@linaro.org> References: <1399363824-23543-1-git-send-email-sachin.kamat@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SRAM binding documentation. Signed-off-by: Sachin Kamat Acked-by: Arnd Bergmann --- No changes since v1. --- .../devicetree/bindings/arm/exynos/smp-sram.txt | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/exynos/smp-sram.txt diff --git a/Documentation/devicetree/bindings/arm/exynos/smp-sram.txt b/Documentation/devicetree/bindings/arm/exynos/smp-sram.txt new file mode 100644 index 000000000000..c9ff2f58f9b6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/exynos/smp-sram.txt @@ -0,0 +1,38 @@ +Samsung Exynos SRAM for SMP bringup: +------------------------------------ + +Samsung SMP-capable Exynos SoCs use part of the SRAM for the bringup +of the secondary cores. Once the core gets powered up it executes the +code that is residing at some specific location of the SRAM. + +Therefore reserved section sub-nodes have to be added to the mmio-sram +declaration. These nodes are of two types depending upon secure or +non-secure execution environment. + +Required sub-node properties: +- compatible : depending upon boot mode, should be + "samsung,exynos4210-sram" : for Secure SYSRAM + "samsung,exynos4210-sram-ns" : for Non-secure SYSRAM + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sram.txt + +Example: + + sram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sram@0 { + compatible = "samsung,exynos4210-sram"; + reg = <0x0 0x1000>; + }; + + smp-sram@53000 { + compatible = "samsung,exynos4210-sram-ns"; + reg = <0x53000 0x1000>; + }; + };