@@ -1250,7 +1250,7 @@ static int ac97_load (QEMUFile *f, void *opaque, int version_id)
}
static void ac97_map (PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev);
PCIDevice *d = &s->dev;
@@ -3170,7 +3170,7 @@ void isa_cirrus_vga_init(void)
***************************************/
static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
@@ -3191,7 +3191,7 @@ static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
}
static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
@@ -142,10 +142,11 @@ static const char phy_regcap[0x20] = {
};
static void
-ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr,
- uint32_t size, int type)
+ioport_map(PCIDevice *pci_dev, int region_num, uint64_t addr,
+ uint64_t size, int type)
{
- DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
+ DBGOUT(IO, "e1000_ioport_map addr=0x%04"PRIx64" size=0x%08"PRIx64"\n",
+ addr, size);
}
static void
@@ -1030,7 +1031,7 @@ static CPUReadMemoryFunc * const e1000_mmio_read[] = {
static void
e1000_mmio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
int i;
@@ -1040,7 +1041,8 @@ e1000_mmio_map(PCIDevice *pci_dev, int region_num,
};
- DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
+ DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"PRIx64" 0x%08"PRIx64"\n",
+ addr, size);
cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
qemu_register_coalesced_mmio(addr, excluded_regs[0]);
@@ -1374,11 +1374,12 @@ static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
/* PCI EEPRO100 definitions */
static void pci_map(PCIDevice * pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
- TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
+ TRACE(OTHER, logout("region %d, addr=0x%08"PRIx64", "
+ "size=0x%08"PRIx64", type=%d\n",
region_num, addr, size, type));
assert(region_num == 1);
@@ -1453,11 +1454,12 @@ static CPUReadMemoryFunc * const pci_mmio_read[] = {
};
static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
- TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
+ TRACE(OTHER, logout("region %d, addr=0x%08"PRIx64", "
+ "size=0x%08"PRIx64", type=%d\n",
region_num, addr, size, type));
if (region_num == 0) {
@@ -907,7 +907,7 @@ static void es1370_adc_callback (void *opaque, int avail)
}
static void es1370_map (PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
ES1370State *s = DO_UPCAST (ES1370State, dev, pci_dev);
@@ -60,7 +60,7 @@ typedef struct PCIIDEState {
static void cmd646_update_irq(PCIIDEState *d);
static void ide_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
PCIIDEState *d = (PCIIDEState *)pci_dev;
IDEBus *bus;
@@ -245,7 +245,7 @@ static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
}
static void bmdma_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
PCIIDEState *d = (PCIIDEState *)pci_dev;
int i;
@@ -1926,7 +1926,7 @@ static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
}
static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);
@@ -1941,7 +1941,7 @@ static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
}
static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);
@@ -1951,7 +1951,7 @@ static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
}
static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);
@@ -40,7 +40,7 @@ struct macio_state_t {
};
static void macio_map (PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
macio_state_t *macio_state;
int i;
@@ -201,7 +201,7 @@ static CPUReadMemoryFunc * const msix_mmio_read[] = {
/* Should be called from device's map method. */
void msix_mmio_map(PCIDevice *d, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
uint8_t *config = d->config + d->msix_cap;
uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
@@ -11,7 +11,7 @@ void msix_write_config(PCIDevice *pci_dev, uint32_t address,
uint32_t val, int len);
void msix_mmio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type);
+ uint64_t addr, uint64_t size, int type);
int msix_uninit(PCIDevice *d);
@@ -715,7 +715,7 @@ static int pci_ne2000_load(QEMUFile* f, void* opaque, int version_id)
/* PCI NE2000 definitions */
static void ne2000_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
NE2000State *s = &d->ne2000;
@@ -1026,7 +1026,7 @@ static CPUReadMemoryFunc * const openpic_read[] = {
};
static void openpic_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
openpic_t *opp;
@@ -396,19 +396,19 @@ int pci_unregister_device(PCIDevice *pci_dev)
}
void pci_register_bar(PCIDevice *pci_dev, int region_num,
- uint32_t size, int type,
+ uint64_t size, int type,
PCIMapIORegionFunc *map_func)
{
PCIIORegion *r;
uint32_t addr;
- uint32_t wmask;
+ uint64_t wmask;
if ((unsigned int)region_num >= PCI_NUM_REGIONS)
return;
if (size & (size-1)) {
fprintf(stderr, "ERROR: PCI region size must be pow2 "
- "type=0x%x, size=0x%x\n", type, size);
+ "type=0x%x, size=0x%"PRIx64"\n", type, size);
exit(1);
}
@@ -427,7 +427,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
addr = 0x10 + region_num * 4;
}
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
- *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
+ *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask & 0xffffffff);
*(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
}
@@ -435,7 +435,8 @@ static void pci_update_mappings(PCIDevice *d)
{
PCIIORegion *r;
int cmd, i;
- uint32_t last_addr, new_addr, config_ofs;
+ uint64_t last_addr, new_addr;
+ uint32_t config_ofs;
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
for(i = 0; i < PCI_NUM_REGIONS; i++) {
@@ -474,7 +475,11 @@ static void pci_update_mappings(PCIDevice *d)
mappings, we handle specific values as invalid
mappings. */
if (last_addr <= new_addr || new_addr == 0 ||
- last_addr == PCI_BAR_UNMAPPED) {
+ last_addr == PCI_BAR_UNMAPPED ||
+
+ /* keep old behaviour
+ * without this, PC ide doesn't work well. */
+ last_addr >= UINT32_MAX) {
new_addr = PCI_BAR_UNMAPPED;
}
} else {
@@ -730,10 +735,10 @@ static void pci_info_device(PCIDevice *d)
if (r->size != 0) {
monitor_printf(mon, " BAR%d: ", i);
if (r->type & PCI_ADDRESS_SPACE_IO) {
- monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
+ monitor_printf(mon, "I/O at 0x%04"PRIx64" [0x%04"PRIx64"].\n",
r->addr, r->addr + r->size - 1);
} else {
- monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
+ monitor_printf(mon, "32 bit memory at 0x%08"PRIx64" [0x%08"PRIx64"].\n",
r->addr, r->addr + r->size - 1);
}
}
@@ -1048,7 +1053,8 @@ static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
r = &d->io_regions[i];
if (!r->size)
continue;
- monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
+ monitor_printf(mon, "%*sbar %d: %s at 0x%"PRIx64" [0x%"PRIx64"]\n",
+ indent, "",
i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
r->addr, r->addr + r->size - 1);
}
@@ -76,7 +76,7 @@ typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
uint32_t address, int len);
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type);
+ uint64_t addr, uint64_t size, int type);
typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
#define PCI_ADDRESS_SPACE_MEM 0x00
@@ -84,9 +84,9 @@ typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
typedef struct PCIIORegion {
- uint32_t addr; /* current PCI mapping address. -1 means not mapped */
-#define PCI_BAR_UNMAPPED (~(uint32_t)0)
- uint32_t size;
+ uint64_t addr; /* current PCI mapping address. -1 means not mapped */
+#define PCI_BAR_UNMAPPED (~(uint64_t)0)
+ uint64_t size;
uint8_t type;
PCIMapIORegionFunc *map_func;
} PCIIORegion;
@@ -230,7 +230,7 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name,
int pci_unregister_device(PCIDevice *pci_dev);
void pci_register_bar(PCIDevice *pci_dev, int region_num,
- uint32_t size, int type,
+ uint64_t size, int type,
PCIMapIORegionFunc *map_func);
int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
@@ -1761,12 +1761,13 @@ static uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr)
}
static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
PCNetState *d = &DO_UPCAST(PCIPCNetState, pci_dev, pci_dev)->state;
#ifdef PCNET_DEBUG_IO
- printf("pcnet_ioport_map addr=0x%04x size=0x%04x\n", addr, size);
+ printf("pcnet_ioport_map addr=0x%04"PRIx64" size=0x%04"PRIx64"\n",
+ addr, size);
#endif
register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
@@ -1989,12 +1990,12 @@ static CPUReadMemoryFunc * const pcnet_mmio_read[] = {
};
static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
#ifdef PCNET_DEBUG_IO
- printf("pcnet_mmio_map addr=0x%08x 0x%08x\n", addr, size);
+ printf("pcnet_mmio_map addr=0x%08"PRIx64" 0x%08"PRIx64"\n", addr, size);
#endif
cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->state.mmio_index);
@@ -3324,7 +3324,7 @@ static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
/* PCI RTL8139 definitions */
static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
@@ -3332,7 +3332,7 @@ static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
}
static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
@@ -344,7 +344,7 @@ static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
switch (region_num) {
@@ -1707,7 +1707,7 @@ typedef struct {
} OHCIPCIState;
static void ohci_mapfunc(PCIDevice *pci_dev, int i,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, pci_dev);
cpu_register_physical_memory(addr, size, ohci->state.mem);
@@ -1059,7 +1059,7 @@ static void uhci_frame_timer(void *opaque)
}
static void uhci_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
UHCIState *s = (UHCIState *)pci_dev;
@@ -71,7 +71,7 @@ void vga_dirty_log_start(VGACommonState *s)
}
static void vga_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
PCIVGAState *d = (PCIVGAState *)pci_dev;
VGACommonState *s = &d->vga;
@@ -342,7 +342,7 @@ static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val)
}
static void virtio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev);
VirtIODevice *vdev = proxy->vdev;
@@ -1174,7 +1174,7 @@ static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
}
static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
struct vmsvga_state_s *s = &d->chip;
@@ -1194,7 +1194,7 @@ static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
}
static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
struct vmsvga_state_s *s = &d->chip;
@@ -347,7 +347,7 @@ static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
}
static void i6300esb_map(PCIDevice *dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ uint64_t addr, uint64_t size, int type)
{
static CPUReadMemoryFunc * const mem_read[3] = {
i6300esb_mem_readb,
@@ -362,7 +362,8 @@ static void i6300esb_map(PCIDevice *dev, int region_num,
I6300State *d = DO_UPCAST(I6300State, dev, dev);
int io_mem;
- i6300esb_debug("addr = %x, size = %x, type = %d\n", addr, size, type);
+ i6300esb_debug("addr = %"PRIx64", size = %"PRIx64", type = %d\n",
+ addr, size, type);
io_mem = cpu_register_io_memory(mem_read, mem_write, d);
cpu_register_physical_memory (addr, 0x10, io_mem);
This patch is preliminary for 64bit bar. For 64bit bar support, replace uint32_t with uint64_t for addr/size to be able to represent 64bit. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> --- hw/ac97.c | 2 +- hw/cirrus_vga.c | 4 ++-- hw/e1000.c | 12 +++++++----- hw/eepro100.c | 10 ++++++---- hw/es1370.c | 2 +- hw/ide/pci.c | 4 ++-- hw/lsi53c895a.c | 6 +++--- hw/macio.c | 2 +- hw/msix.c | 2 +- hw/msix.h | 2 +- hw/ne2000.c | 2 +- hw/openpic.c | 2 +- hw/pci.c | 24 +++++++++++++++--------- hw/pci.h | 10 +++++----- hw/pcnet.c | 9 +++++---- hw/rtl8139.c | 4 ++-- hw/sun4u.c | 2 +- hw/usb-ohci.c | 2 +- hw/usb-uhci.c | 2 +- hw/vga-pci.c | 2 +- hw/virtio-pci.c | 2 +- hw/vmware_vga.c | 4 ++-- hw/wdt_i6300esb.c | 5 +++-- 23 files changed, 64 insertions(+), 52 deletions(-)