Patchwork [45/61] pci/monitor: print out bridge's filtering values and so on.

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Submitter Isaku Yamahata
Date Sept. 30, 2009, 10:18 a.m.
Message ID <1254305917-14784-46-git-send-email-yamahata@valinux.co.jp>
Download mbox | patch
Permalink /patch/34593/
State Superseded
Headers show

Comments

Isaku Yamahata - Sept. 30, 2009, 10:18 a.m.
make pci_info_device() print out bridge's filtering value like
io base/limit, subbus and subordinate bus.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pci.c |   43 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 43 insertions(+), 0 deletions(-)

Patch

diff --git a/hw/pci.c b/hw/pci.c
index 94fe87f..7aed737 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1150,7 +1150,50 @@  static void pci_info_device(PCIDevice *d)
                        d->config[PCI_INTERRUPT_LINE]);
     }
     if (class == 0x0604) {
+        int shift;
+        uint64_t base;
+        uint64_t limit;
         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
+        monitor_printf(mon, "      SECONDARY BUS %d.\n",
+                       d->config[PCI_SECONDARY_BUS]);
+        monitor_printf(mon, "      SUBORDINATE BUS %d.\n",
+                       d->config[PCI_SUBORDINATE_BUS]);
+
+        if (d->config[PCI_IO_BASE] & PCI_IO_RANGE_TYPE_32) {
+            shift = 16;
+        } else {
+            shift = 8;
+        }
+        base = ((uint32_t)d->config[PCI_IO_BASE] & ~PCI_IO_RANGE_TYPE_MASK)
+            << shift;
+        base |= (uint32_t)pci_config_get_word(d, PCI_IO_BASE_UPPER16) << 16;
+        limit = ((uint32_t)d->config[PCI_IO_LIMIT] & ~PCI_IO_RANGE_TYPE_MASK)
+            << shift;
+        limit |= (uint32_t)pci_config_get_word(d, PCI_IO_LIMIT_UPPER16) << 16;
+        limit |= 0xfff;
+        monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
+                       base, limit);
+
+        shift = 16;
+        base = ((uint32_t)pci_config_get_word(d, PCI_MEMORY_BASE) &
+                PCI_MEMORY_RANGE_MASK) << shift;
+        limit = ((uint32_t)pci_config_get_word(d, PCI_MEMORY_LIMIT) &
+                 PCI_MEMORY_RANGE_MASK) << shift;
+        limit |= 0xfffff;
+        monitor_printf(mon,
+                       "      MEM range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
+                       base, limit);
+        shift = 16;
+        base = ((uint64_t)pci_config_get_word(d, PCI_PREF_MEMORY_BASE) &
+                PCI_PREF_RANGE_MASK) << shift;
+        limit = ((uint64_t)pci_config_get_word(d, PCI_PREF_MEMORY_LIMIT) &
+                 PCI_PREF_RANGE_MASK) << shift;
+        base |= (uint64_t)pci_config_get_long(d, PCI_PREF_BASE_UPPER32) << 32;
+        limit |= (uint64_t)pci_config_get_long(d, PCI_PREF_LIMIT_UPPER32) << 32;
+        limit |= 0xfffff;
+        monitor_printf(mon,
+                       "      pref MEM range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
+                       base, limit);
     }
     for(i = 0;i < PCI_NUM_REGIONS; i++) {
         r = &d->io_regions[i];