@@ -33,6 +33,8 @@
#endif
#define IOAPIC_NUM_PINS_DEFAULT 0x18
+#define IOAPIC_NUM_PINS_MIN 16
+#define IOAPIC_NUM_PINS_MAX 240
#define IOAPIC_LVT_MASKED (1<<16)
#define IOAPIC_TRIGGER_EDGE 0
@@ -52,7 +54,7 @@ struct IOAPICState {
uint8_t id;
uint8_t ioregsel;
- uint32_t irr;
+ uint8_t *irr;
uint64_t *ioredtbl;
ioapic_update_fn update_fn;
void *opaque;
@@ -64,21 +66,39 @@ static void ioapic_callback(IOAPICState *s, int reset)
s->update_fn(s->opaque, reset);
}
+static int ioapic_irr_is_set(IOAPICState *s, int vector)
+{
+ return (s->irr[vector / 8] & (1 << (vector % 8)));
+}
+
+static void ioapic_irr_set(IOAPICState *s, int vector)
+{
+ s->irr[vector / 8] |= (1 << (vector % 8));
+}
+
+static void ioapic_irr_clear(IOAPICState *s, int vector)
+{
+ s->irr[vector / 8] &= ~(1 << (vector % 8));
+}
+
+static size_t ioapic_irr_size(int num_pins)
+{
+ return (num_pins + 7) / 8 * sizeof(uint8_t);
+}
+
static void ioapic_service(IOAPICState *s)
{
uint8_t i;
uint8_t trig_mode;
uint8_t vector;
uint8_t delivery_mode;
- uint32_t mask;
uint64_t entry;
uint8_t dest;
uint8_t dest_mode;
uint8_t polarity;
for (i = 0; i < s->num_pins; i++) {
- mask = 1 << i;
- if (s->irr & mask) {
+ if (ioapic_irr_is_set(s, i)) {
entry = s->ioredtbl[i];
if (!(entry & IOAPIC_LVT_MASKED)) {
trig_mode = ((entry >> 15) & 1);
@@ -87,7 +107,7 @@ static void ioapic_service(IOAPICState *s)
delivery_mode = (entry >> 8) & 7;
polarity = (entry >> 13) & 1;
if (trig_mode == IOAPIC_TRIGGER_EDGE)
- s->irr &= ~mask;
+ ioapic_irr_clear(s, i);
if (delivery_mode == IOAPIC_DM_EXTINT)
vector = pic_read_irq(isa_pic);
else
@@ -112,21 +132,20 @@ static void ioapic_set_irq(void *opaque, int vector, int level)
vector = 2;
if (vector >= 0 && vector < s->num_pins) {
- uint32_t mask = 1 << vector;
uint64_t entry = s->ioredtbl[vector];
if ((entry >> 15) & 1) {
/* level triggered */
if (level) {
- s->irr |= mask;
+ ioapic_irr_set(s, vector);
ioapic_service(s);
} else {
- s->irr &= ~mask;
+ ioapic_irr_clear(s, vector);
}
} else {
/* edge triggered */
if (level) {
- s->irr |= mask;
+ ioapic_irr_set(s, vector);
ioapic_service(s);
}
}
@@ -239,7 +258,7 @@ static void ioapic_reset(void *opaque)
s->id = 0;
s->ioregsel = 0;
- s->irr = 0;
+ memset(s->irr, 0, ioapic_irr_size(s->num_pins));
for(i = 0; i < s->num_pins; i++)
s->ioredtbl[i] = 1 << 16; /* mask LVT */
}
@@ -263,11 +282,14 @@ static void ioapic_init_with_arg(uint8_t num_pins,
IOAPICState *s;
int io_memory;
+ assert(IOAPIC_NUM_PINS_MIN <= num_pins);
+ assert(num_pins <= IOAPIC_NUM_PINS_MAX);
s = qemu_mallocz(sizeof(*s));
*sp = s;
- s->ioredtbl = qemu_mallocz(sizeof(s->ioredtbl[0]) * num_pins);
s->num_pins = num_pins;
+ s->irr = qemu_mallocz(ioapic_irr_size(num_pins));
+ s->ioredtbl = qemu_mallocz(sizeof(s->ioredtbl[0]) * num_pins);
s->update_fn = update_fn;
s->opaque = opaque;
ioapic_reset(s);
make irr accept more than 32 pins. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> --- hw/ioapic.c | 44 +++++++++++++++++++++++++++++++++----------- 1 files changed, 33 insertions(+), 11 deletions(-)