Patchwork [v1,1/4] target-arm: Make vbar_write 64bit friendly on 32bit hosts

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Submitter Edgar Iglesias
Date May 1, 2014, 6:34 a.m.
Message ID <1398926097-28097-2-git-send-email-edgar.iglesias@gmail.com>
Download mbox | patch
Permalink /patch/344441/
State New
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Comments

Edgar Iglesias - May 1, 2014, 6:34 a.m.
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
alex.bennee@linaro.org - May 1, 2014, 9:04 a.m.
Edgar E. Iglesias <edgar.iglesias@gmail.com> writes:

> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  target-arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 43c1b4f..330bfc7 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -657,7 +657,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
>       * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
>       * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
>       */
> -    env->cp15.c12_vbar = value & ~0x1Ful;
> +    env->cp15.c12_vbar = value & ~0x1FULL;
>  }
>  
>  static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
Peter Crosthwaite - May 1, 2014, 12:55 p.m.
On Thu, May 1, 2014 at 4:34 PM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  target-arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 43c1b4f..330bfc7 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -657,7 +657,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
>       * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
>       * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
>       */
> -    env->cp15.c12_vbar = value & ~0x1Ful;
> +    env->cp15.c12_vbar = value & ~0x1FULL;
>  }
>
>  static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> --
> 1.8.3.2
>
>

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 43c1b4f..330bfc7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -657,7 +657,7 @@  static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
      */
-    env->cp15.c12_vbar = value & ~0x1Ful;
+    env->cp15.c12_vbar = value & ~0x1FULL;
 }
 
 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)