From patchwork Wed Apr 30 21:50:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin O'Connor X-Patchwork-Id: 344342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43A89140107 for ; Thu, 1 May 2014 07:51:12 +1000 (EST) Received: from localhost ([::1]:59396 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfcPG-0001jW-AG for incoming@patchwork.ozlabs.org; Wed, 30 Apr 2014 17:51:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60755) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfcOs-0001RF-BS for qemu-devel@nongnu.org; Wed, 30 Apr 2014 17:50:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WfcOm-0005NN-7L for qemu-devel@nongnu.org; Wed, 30 Apr 2014 17:50:46 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:33523) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfcOl-0005N9-Of for qemu-devel@nongnu.org; Wed, 30 Apr 2014 17:50:39 -0400 Received: by mail-pa0-f50.google.com with SMTP id rd3so2689585pab.37 for ; Wed, 30 Apr 2014 14:50:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-type:content-disposition:in-reply-to :user-agent; bh=eK6HVg+I9jDP2yyf5Qy93N2IwvB7He0CM0cFDMyzfR4=; b=CqjnEjaoFyfzvDnVBvWonscrKVmHO/V3mBcTI8kZJRVTkMGSnbKiP9/z+AITshrgY0 R/HwLXbD9XWW7bwypelq+1CvIL6O2eAFzXg9+7VbI0k5A2R0mwhATGWkvW6o+HXVNZzV ELI1fPuzCtXEADS0nOf4MRS/vLGkgBdvHckT4WYnmEGVzwLJioV2EbntTUYLG8CkVsW7 wgSmQsYKp6dXpKZPlcrYG5ZozGgpLZqlrUImYpnTkwTcj1wuG/QQVpZOgm880k6WvcJ3 +c6IwuFeapnesG51C/hcie0axMTSUzNPf1s4+cmulzXGgNt8H3pWXbMbA26i6dT/cwns tpNQ== X-Gm-Message-State: ALoCoQkEk+pdoqDEtR90k00b111Rh7Zy7Ppkoy3kbO4MIF5WsJTnh437R7Q0FjVw0NwB7VF+8Bhz X-Received: by 10.66.189.201 with SMTP id gk9mr13267110pac.25.1398894635741; Wed, 30 Apr 2014 14:50:35 -0700 (PDT) Received: from localhost ([207.172.170.53]) by mx.google.com with ESMTPSA id vo1sm144028706pab.32.2014.04.30.14.50.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Apr 2014 14:50:35 -0700 (PDT) Date: Wed, 30 Apr 2014 17:50:09 -0400 From: Kevin O'Connor To: Richard Henderson , Paolo Bonzini Message-ID: <20140430215008.GC30435@morn.localdomain> References: <52b90f04f7c81f5627a9adba9459322d92bf3706.1398802891.git.kevin@koconnor.net> <53612AB2.1050808@twiddle.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <53612AB2.1050808@twiddle.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.50 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCHv3 2/4] Set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Wed, Apr 30, 2014 at 09:54:10AM -0700, Richard Henderson wrote: > On 04/29/2014 01:38 PM, Kevin O'Connor wrote: > > cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | > > DF_MASK)); > > env->eip = 0x00008000; > > + cpu_x86_update_cr0(env, > > + env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | > > + CR0_PG_MASK)); > > + cpu_x86_update_cr4(env, 0); > > + env->dr[7] = 0x00000400; > > + CC_OP = CC_OP_EFLAGS; > > Please place the CC_OP update immediately after cpu_load_eflags. Sure - see below. Paolo, if this conflicts with your work, you can use the previous version of this patch. -Kevin From 12abb36264ac441444d21efa382bacc9f8b657ca Mon Sep 17 00:00:00 2001 Message-Id: <12abb36264ac441444d21efa382bacc9f8b657ca.1398894385.git.kevin@koconnor.net> In-Reply-To: References: From: Kevin O'Connor Date: Tue, 29 Apr 2014 11:19:06 -0400 Subject: [PATCH 2/4] Set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c. To: qemu-devel@nongnu.org The cpu_x86_load_seg_cache() function inspects cr0 and eflags, so make sure all changes to eflags and cr0 are done prior to loading the segment caches. Signed-off-by: Kevin O'Connor --- target-i386/smm_helper.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 35901c9..5b36f3f 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -162,7 +162,14 @@ void do_smm_enter(X86CPU *cpu) #endif cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); + CC_OP = CC_OP_EFLAGS; env->eip = 0x00008000; + cpu_x86_update_cr0(env, + env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | + CR0_PG_MASK)); + cpu_x86_update_cr4(env, 0); + env->dr[7] = 0x00000400; + cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase, 0xffffffff, 0); cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0); @@ -170,13 +177,6 @@ void do_smm_enter(X86CPU *cpu) cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0); cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0); cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0); - - cpu_x86_update_cr0(env, - env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | - CR0_PG_MASK)); - cpu_x86_update_cr4(env, 0); - env->dr[7] = 0x00000400; - CC_OP = CC_OP_EFLAGS; } void helper_rsm(CPUX86State *env) @@ -191,16 +191,6 @@ void helper_rsm(CPUX86State *env) #ifdef TARGET_X86_64 cpu_load_efer(env, ldq_phys(cs->as, sm_state + 0x7ed0)); - for (i = 0; i < 6; i++) { - offset = 0x7e00 + i * 16; - cpu_x86_load_seg_cache(env, i, - lduw_phys(cs->as, sm_state + offset), - ldq_phys(cs->as, sm_state + offset + 8), - ldl_phys(cs->as, sm_state + offset + 4), - (lduw_phys(cs->as, sm_state + offset + 2) & - 0xf0ff) << 8); - } - env->gdt.base = ldq_phys(cs->as, sm_state + 0x7e68); env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7e64); @@ -238,6 +228,16 @@ void helper_rsm(CPUX86State *env) cpu_x86_update_cr3(env, ldl_phys(cs->as, sm_state + 0x7f50)); cpu_x86_update_cr0(env, ldl_phys(cs->as, sm_state + 0x7f58)); + for (i = 0; i < 6; i++) { + offset = 0x7e00 + i * 16; + cpu_x86_load_seg_cache(env, i, + lduw_phys(cs->as, sm_state + offset), + ldq_phys(cs->as, sm_state + offset + 8), + ldl_phys(cs->as, sm_state + offset + 4), + (lduw_phys(cs->as, sm_state + offset + 2) & + 0xf0ff) << 8); + } + val = ldl_phys(cs->as, sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { env->smbase = ldl_phys(cs->as, sm_state + 0x7f00) & ~0x7fff;