From patchwork Wed Apr 30 19:41:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gabriel L. 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[128.2.16.43]) by mx.google.com with ESMTPSA id l61sm31949184qge.11.2014.04.30.12.41.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Apr 2014 12:41:10 -0700 (PDT) X-Google-Original-From: "Gabriel L. Somlo" Date: Wed, 30 Apr 2014 15:41:08 -0400 From: "Gabriel L. Somlo" To: qemu-devel@nongnu.org Message-ID: <20140430194108.GB16023@ERROL.INI.CMU.EDU> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <53614CF2.5060505@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::230 Cc: pbonzini@redhat.com, agraf@suse.de, afaerber@suse.de, mst@redhat.com Subject: [Qemu-devel] [PATCH v3] apic: bump emulated lapic version to 0x14 on pc machines >= 2.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Some guests (e.g. 0S X) more or less arbitrarily insist on a minimum lapic version of 0x14 in order to successfully boot. This patch bumps the emulated apic version on piix and q35 machine types >= 2.1. Signed-off-by: Gabriel L. Somlo --- On Wed, Apr 30, 2014 at 09:20:18PM +0200, Paolo Bonzini wrote: > I think it's preferrable to have apic_version be a device property > with a default of 0x14, and use the compat_props to make it 0x11 on > older machine types. You mean, flip everything around, like below ? Thanks, Gabriel hw/i386/pc_piix.c | 7 +++++++ hw/i386/pc_q35.c | 7 +++++++ hw/intc/apic.c | 4 +++- include/hw/i386/apic.h | 2 ++ 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 5b3594b..d90ce5a 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -29,6 +29,7 @@ #include "hw/i386/pc.h" #include "hw/i386/apic.h" #include "hw/i386/smbios.h" +#include "hw/i386/apic.h" #include "hw/pci/pci.h" #include "hw/pci/pci_ids.h" #include "hw/usb.h" @@ -62,6 +63,7 @@ static bool has_pci_info; static bool has_acpi_build = true; static bool smbios_defaults = true; static bool smbios_legacy_mode; +static bool soft_apic_compat; /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte * pages in the host. @@ -102,6 +104,10 @@ static void pc_init1(QEMUMachineInitArgs *args, exit(1); } + if (soft_apic_compat) { + apic_version = 0x11; + } + icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); object_property_add_child(qdev_get_machine(), "icc-bridge", OBJECT(icc_bridge), NULL); @@ -266,6 +272,7 @@ static void pc_init_pci(QEMUMachineInitArgs *args) static void pc_compat_2_0(QEMUMachineInitArgs *args) { smbios_legacy_mode = true; + soft_apic_compat = true; } static void pc_compat_1_7(QEMUMachineInitArgs *args) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 5b48231..8db0edb 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -40,6 +40,7 @@ #include "exec/address-spaces.h" #include "hw/i386/ich9.h" #include "hw/i386/smbios.h" +#include "hw/i386/apic.h" #include "hw/ide/pci.h" #include "hw/ide/ahci.h" #include "hw/usb.h" @@ -52,6 +53,7 @@ static bool has_pci_info; static bool has_acpi_build = true; static bool smbios_defaults = true; static bool smbios_legacy_mode; +static bool soft_apic_compat; /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte * pages in the host. @@ -89,6 +91,10 @@ static void pc_q35_init(QEMUMachineInitArgs *args) exit(1); } + if (soft_apic_compat) { + apic_version = 0x11; + } + icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); object_property_add_child(qdev_get_machine(), "icc-bridge", OBJECT(icc_bridge), NULL); @@ -244,6 +250,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args) static void pc_compat_2_0(QEMUMachineInitArgs *args) { smbios_legacy_mode = true; + soft_apic_compat = true; } static void pc_compat_1_7(QEMUMachineInitArgs *args) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 2f40cba..4480bc4 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -32,6 +32,8 @@ #define SYNC_TO_VAPIC 0x2 #define SYNC_ISR_IRR_TO_VAPIC 0x4 +uint8_t apic_version = 0x14; + static APICCommonState *local_apics[MAX_APICS + 1]; static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); @@ -675,7 +677,7 @@ static uint32_t apic_mem_readl(void *opaque, hwaddr addr) val = s->id << 24; break; case 0x03: /* version */ - val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ + val = apic_version | ((APIC_LVT_NB - 1) << 16); break; case 0x08: apic_sync_vapic(s, SYNC_FROM_VAPIC); diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index 1d48e02..4e79240 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -4,6 +4,8 @@ #include "qemu-common.h" /* apic.c */ +extern uint8_t apic_version; + void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode); int apic_accept_pic_intr(DeviceState *s);