diff mbox

[U-Boot,02/12] SPL: NAND: add support for mxs nand

Message ID 1398716258-8420-3-git-send-email-tharvey@gateworks.com
State Changes Requested
Delegated to: Stefano Babic
Headers show

Commit Message

Tim Harvey April 28, 2014, 8:17 p.m. UTC
This utilizes existing mxs_nand support layer to provide a method to load an
image off nand for SPL. The flash device will be detected in order to support
multiple flash devices instead of having layout hard coded at build time.

Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
v2:
- remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base
  and nand_bbt to bring SPL down in size. This reduced codesize by about 32k
  where now mxs_spl_nand is about 12k total.
---
 drivers/mtd/nand/Makefile       |   1 +
 drivers/mtd/nand/mxs_nand_spl.c | 239 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 240 insertions(+)
 create mode 100644 drivers/mtd/nand/mxs_nand_spl.c

Comments

Scott Wood May 2, 2014, 8:56 p.m. UTC | #1
On Mon, 2014-04-28 at 13:17 -0700, Tim Harvey wrote:
> +static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
> +			     int column, int page_addr)
> +{
> +	register struct nand_chip *chip = mtd->priv;
> +	int ctrl = NAND_NCE | NAND_CTRL_CLE | NAND_CTRL_CHANGE;
> +	u32 timeo, time_start;
> +
> +	/* write out the command to the device */
> +	chip->cmd_ctrl(mtd, command, ctrl);
> +
> +	/* Address cycle, when necessary */
> +	ctrl = NAND_NCE | NAND_CTRL_ALE | NAND_CTRL_CHANGE;
> +	/* Serially input address */
> +	if (column != -1) {
> +		ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;

What happened to NAND_NCE?

It looks like the cmd_ctrl in nand_mxs.c doesn't care about NAND_MCE at
all, so there's no functional impact, but either use it consistently or
don't use it at all.

> +		chip->cmd_ctrl(mtd, column, ctrl);
> +		ctrl &= ~NAND_CTRL_CHANGE;
> +		chip->cmd_ctrl(mtd, column >> 8, ctrl);
> +	}

Why not pass the ctrl flags directly to cmd_ctrl as you do in most of
the rest of the function?  nand_mxs.c doesn't even look at NAND_CTRL_CHANGE.

> +int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
> +{
> +	register struct nand_chip *chip;

Why "register"?

> +		if (!(page % nand_page_per_block)) {
> +			/*
> +			 * Yes, new block. See if this block is good. If not,
> +			 * loop until we find a good block.
> +			 */
> +			while (is_badblock(&mtd, offs, 1)) {
> +				page = page + nand_page_per_block;
> +				/* Check i we've reached the end of flash. */
> +				if (page >= mtd.size >> chip->page_shift)
> +					return -1;

Why -1 rather than a real error value?

-Scott
Tim Harvey May 6, 2014, 4:08 a.m. UTC | #2
On Fri, May 2, 2014 at 1:56 PM, Scott Wood <scottwood@freescale.com> wrote:

Hi Scott,

> On Mon, 2014-04-28 at 13:17 -0700, Tim Harvey wrote:
>> +static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
>> +                          int column, int page_addr)
>> +{
>> +     register struct nand_chip *chip = mtd->priv;
>> +     int ctrl = NAND_NCE | NAND_CTRL_CLE | NAND_CTRL_CHANGE;
>> +     u32 timeo, time_start;
>> +
>> +     /* write out the command to the device */
>> +     chip->cmd_ctrl(mtd, command, ctrl);
>> +
>> +     /* Address cycle, when necessary */
>> +     ctrl = NAND_NCE | NAND_CTRL_ALE | NAND_CTRL_CHANGE;
>> +     /* Serially input address */
>> +     if (column != -1) {
>> +             ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
>
> What happened to NAND_NCE?
>
> It looks like the cmd_ctrl in nand_mxs.c doesn't care about NAND_MCE at
> all, so there's no functional impact, but either use it consistently or
> don't use it at all.
>
>> +             chip->cmd_ctrl(mtd, column, ctrl);
>> +             ctrl &= ~NAND_CTRL_CHANGE;
>> +             chip->cmd_ctrl(mtd, column >> 8, ctrl);
>> +     }
>
> Why not pass the ctrl flags directly to cmd_ctrl as you do in most of
> the rest of the function?  nand_mxs.c doesn't even look at NAND_CTRL_CHANGE.

I'll simplify using only what nand_mxs.c pays attention to (NAND_ALE,
NAND_CLE), remove the ctrl var and repost

>
>> +int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
>> +{
>> +     register struct nand_chip *chip;
>
> Why "register"?

cut-n-paste code from nand_base.c - will remove

>
>> +             if (!(page % nand_page_per_block)) {
>> +                     /*
>> +                      * Yes, new block. See if this block is good. If not,
>> +                      * loop until we find a good block.
>> +                      */
>> +                     while (is_badblock(&mtd, offs, 1)) {
>> +                             page = page + nand_page_per_block;
>> +                             /* Check i we've reached the end of flash. */
>> +                             if (page >= mtd.size >> chip->page_shift)
>> +                                     return -1;
>
> Why -1 rather than a real error value?

probably from the example I used from drivers/mtd/nand/mxc_nand_spl.c.
The calling functions don't appear to do any error checking, but I'll
replace it with -ENOMEM and -ENODEV if mxs_nand_init() fails.

Thanks for the review!

Tim

>
> -Scott
>
>
diff mbox

Patch

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 02b149c..de5b461 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -65,5 +65,6 @@  else  # minimal SPL drivers
 obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
+obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
 
 endif # drivers
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
new file mode 100644
index 0000000..82491a4
--- /dev/null
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -0,0 +1,239 @@ 
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <nand.h>
+#include <malloc.h>
+
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
+			     int column, int page_addr)
+{
+	register struct nand_chip *chip = mtd->priv;
+	int ctrl = NAND_NCE | NAND_CTRL_CLE | NAND_CTRL_CHANGE;
+	u32 timeo, time_start;
+
+	/* write out the command to the device */
+	chip->cmd_ctrl(mtd, command, ctrl);
+
+	/* Address cycle, when necessary */
+	ctrl = NAND_NCE | NAND_CTRL_ALE | NAND_CTRL_CHANGE;
+	/* Serially input address */
+	if (column != -1) {
+		ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
+		chip->cmd_ctrl(mtd, column, ctrl);
+		ctrl &= ~NAND_CTRL_CHANGE;
+		chip->cmd_ctrl(mtd, column >> 8, ctrl);
+	}
+	if (page_addr != -1) {
+		chip->cmd_ctrl(mtd, page_addr, ctrl);
+		chip->cmd_ctrl(mtd, page_addr >> 8, NAND_NCE | NAND_ALE);
+		/* One more address cycle for devices > 128MiB */
+		if (chip->chipsize > (128 << 20))
+			chip->cmd_ctrl(mtd, page_addr >> 16,
+				       NAND_NCE | NAND_ALE);
+	}
+	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+	if (command == NAND_CMD_READ0) {
+		chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
+			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
+			       NAND_NCE | NAND_CTRL_CHANGE);
+	}
+
+	/* wait for nand ready */
+	ndelay(100);
+	timeo = (CONFIG_SYS_HZ * 20) / 1000;
+	time_start = get_timer(0);
+	while (get_timer(time_start) < timeo) {
+		if (chip->dev_ready(mtd))
+			break;
+	}
+}
+
+static int mxs_flash_ident(struct mtd_info *mtd)
+{
+	register struct nand_chip *chip = mtd->priv;
+	int i;
+	u8 mfg_id, dev_id;
+	u8 id_data[8];
+	struct nand_onfi_params *p = &chip->onfi_params;
+
+	/* Reset the chip */
+	chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+	/* Send the command for reading device ID */
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+	/* Read manufacturer and device IDs */
+	mfg_id = chip->read_byte(mtd);
+	dev_id = chip->read_byte(mtd);
+
+	/* Try again to make sure */
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+	for (i = 0; i < 8; i++)
+		id_data[i] = chip->read_byte(mtd);
+	if (id_data[0] != mfg_id || id_data[1] != dev_id) {
+		printf("second ID read did not match");
+		return -1;
+	}
+	debug("0x%02x:0x%02x ", mfg_id, dev_id);
+
+	/* read ONFI */
+	chip->onfi_version = 0;
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+	if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
+	    chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') {
+		return -2;
+	}
+
+	/* we have ONFI, probe it */
+	chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+	chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
+	mtd->name = p->model;
+	mtd->writesize = le32_to_cpu(p->byte_per_page);
+	mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
+	mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
+	chip->chipsize = le32_to_cpu(p->blocks_per_lun);
+	chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
+	/* Calculate the address shift from the page size */
+	chip->page_shift = ffs(mtd->writesize) - 1;
+	chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
+	/* Convert chipsize to number of pages per chip -1 */
+	chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+	chip->badblockbits = 8;
+
+	debug("erasesize=%d (>>%d)\n", mtd->erasesize, chip->phys_erase_shift);
+	debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift);
+	debug("oobsize=%d\n", mtd->oobsize);
+	debug("chipsize=%lld\n", chip->chipsize);
+
+	return 0;
+}
+
+static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page)
+{
+	register struct nand_chip *chip = mtd->priv;
+	int ret;
+
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page);
+	ret = nand_chip.ecc.read_page(mtd, chip, buf, 1, page);
+	if (ret < 0) {
+		printf("read_page failed %d\n", ret);
+		return -1;
+	}
+	return 0;
+}
+
+static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt)
+{
+	register struct nand_chip *chip = mtd->priv;
+	unsigned int block = offs >> chip->phys_erase_shift;
+	unsigned int page = offs >> chip->page_shift;
+
+	debug("%s offs=0x%08x block:%d page:%d\n", __func__, (int)offs, block,
+	      page);
+	chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+	memset(chip->oob_poi, 0, mtd->oobsize);
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	return (chip->oob_poi[0] != 0xff);
+}
+
+/* setup mtd and nand structs and init mxs_nand driver */
+static int mxs_nand_init(void)
+{
+	/* return if already initalized */
+	if (nand_chip.numchips)
+		return 0;
+
+	/* init mxs nand driver */
+	board_nand_init(&nand_chip);
+	mtd.priv = &nand_chip;
+	/* set mtd functions */
+	nand_chip.cmdfunc = mxs_nand_command;
+	nand_chip.numchips = 1;
+
+	/* identify flash device */
+	puts("NAND : ");
+	if (mxs_flash_ident(&mtd)) {
+		printf("Failed to identify\n");
+		return -1;
+	}
+
+	/* allocate and initialize buffers */
+	nand_chip.buffers = memalign(ARCH_DMA_MINALIGN,
+				     sizeof(*nand_chip.buffers));
+	nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize;
+	/* setup flash layout (does not scan as we override that) */
+	mtd.size = nand_chip.chipsize;
+	nand_chip.scan_bbt(&mtd);
+
+	printf("%llu MiB\n", (mtd.size / (1024 * 1024)));
+	return 0;
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
+{
+	register struct nand_chip *chip;
+	unsigned int page;
+	unsigned int nand_page_per_block;
+	unsigned int sz = 0;
+
+	if (mxs_nand_init())
+		return -1;
+	chip = mtd.priv;
+	page = offs >> chip->page_shift;
+	nand_page_per_block = mtd.erasesize / mtd.writesize;
+
+	debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page);
+
+	size = roundup(size, mtd.writesize);
+	while (sz < size) {
+		if (mxs_read_page_ecc(&mtd, buf, page) < 0)
+			return -1;
+		sz += mtd.writesize;
+		offs += mtd.writesize;
+		page++;
+		buf += mtd.writesize;
+
+		/*
+		 * Check if we have crossed a block boundary, and if so
+		 * check for bad block.
+		 */
+		if (!(page % nand_page_per_block)) {
+			/*
+			 * Yes, new block. See if this block is good. If not,
+			 * loop until we find a good block.
+			 */
+			while (is_badblock(&mtd, offs, 1)) {
+				page = page + nand_page_per_block;
+				/* Check i we've reached the end of flash. */
+				if (page >= mtd.size >> chip->page_shift)
+					return -1;
+			}
+		}
+	}
+
+	return 0;
+}
+
+int nand_default_bbt(struct mtd_info *mtd)
+{
+	return 0;
+}
+
+void nand_init(void)
+{
+}
+
+void nand_deselect(void)
+{
+}
+