From patchwork Fri Sep 25 19:42:33 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerd Hoffmann X-Patchwork-Id: 34287 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 001F4B7BC0 for ; Sat, 26 Sep 2009 05:54:31 +1000 (EST) Received: from localhost ([127.0.0.1]:49101 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MrGs9-0001oC-46 for incoming@patchwork.ozlabs.org; Fri, 25 Sep 2009 15:54:29 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MrGhA-0006QG-QF for qemu-devel@nongnu.org; Fri, 25 Sep 2009 15:43:08 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MrGh4-0006L0-7D for qemu-devel@nongnu.org; Fri, 25 Sep 2009 15:43:07 -0400 Received: from [199.232.76.173] (port=56041 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MrGh3-0006KR-FJ for qemu-devel@nongnu.org; Fri, 25 Sep 2009 15:43:01 -0400 Received: from mx1.redhat.com ([209.132.183.28]:18020) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MrGh3-0004d7-01 for qemu-devel@nongnu.org; Fri, 25 Sep 2009 15:43:01 -0400 Received: from int-mx04.intmail.prod.int.phx2.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.17]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n8PJh0uY027794 for ; Fri, 25 Sep 2009 15:43:00 -0400 Received: from zweiblum.home.kraxel.org (vpn2-8-108.ams2.redhat.com [10.36.8.108]) by int-mx04.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id n8PJguZS004602; Fri, 25 Sep 2009 15:42:57 -0400 Received: by zweiblum.home.kraxel.org (Postfix, from userid 500) id 638E0700E5; Fri, 25 Sep 2009 21:42:50 +0200 (CEST) From: Gerd Hoffmann To: qemu-devel@nongnu.org Date: Fri, 25 Sep 2009 21:42:33 +0200 Message-Id: <1253907769-1067-9-git-send-email-kraxel@redhat.com> In-Reply-To: <1253907769-1067-1-git-send-email-kraxel@redhat.com> References: <1253907769-1067-1-git-send-email-kraxel@redhat.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.17 X-detected-operating-system: by monty-python.gnu.org: Genre and OS details not recognized. Cc: Gerd Hoffmann Subject: [Qemu-devel] [PATCH 08/24] piix_pci: kill PIIX3IrqState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The splitted init + irq setup for the pci bus untangles a initialization order issue and allows to remove the PIIX3IrqState struct. We can carry the state directly in PIIX3State insted. Signed-off-by: Gerd Hoffmann --- hw/piix_pci.c | 37 +++++++++++++++++-------------------- 1 files changed, 17 insertions(+), 20 deletions(-) diff --git a/hw/piix_pci.c b/hw/piix_pci.c index edd6df0..0be3b02 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -36,18 +36,14 @@ typedef PCIHostState I440FXState; typedef struct PIIX3State { PCIDevice dev; int pci_irq_levels[4]; -} PIIX3State; - -typedef struct PIIX3IrqState { - PIIX3State *piix3; qemu_irq *pic; -} PIIX3IrqState; +} PIIX3State; struct PCII440FXState { PCIDevice dev; target_phys_addr_t isa_page_descs[384 / 4]; uint8_t smm_enabled; - PIIX3IrqState *irq_state; + PIIX3State *piix3; }; static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val) @@ -167,7 +163,7 @@ static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) if (version_id == 2) for (i = 0; i < 4; i++) - d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f); + d->piix3->pci_irq_levels[i] = qemu_get_be32(f); return 0; } @@ -232,23 +228,24 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq * PCIBus *b; PCIDevice *d; I440FXState *s; - PIIX3IrqState *irq_state = qemu_malloc(sizeof(*irq_state)); + PIIX3State *piix3; - irq_state->pic = pic; dev = qdev_create(NULL, "i440FX-pcihost"); s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); - b = pci_register_bus(&s->busdev.qdev, "pci.0", - piix3_set_irq, pci_slot_get_pirq, irq_state, 0, 4); + b = pci_bus_new(&s->busdev.qdev, NULL, 0); s->bus = b; qdev_init(dev); d = pci_create_simple(b, 0, "i440FX"); *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); - (*pi440fx_state)->irq_state = irq_state; - irq_state->piix3 = DO_UPCAST(PIIX3State, dev, + piix3 = DO_UPCAST(PIIX3State, dev, pci_create_simple(b, -1, "PIIX3")); - *piix3_devfn = irq_state->piix3->dev.devfn; + piix3->pic = pic; + pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4); + (*pi440fx_state)->piix3 = piix3; + + *piix3_devfn = piix3->dev.devfn; return b; } @@ -258,22 +255,22 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq * static void piix3_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - PIIX3IrqState *irq_state = opaque; + PIIX3State *piix3 = opaque; - irq_state->piix3->pci_irq_levels[irq_num] = level; + piix3->pci_irq_levels[irq_num] = level; /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ - pic_irq = irq_state->piix3->dev.config[0x60 + irq_num]; + pic_irq = piix3->dev.config[0x60 + irq_num]; if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to it */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == irq_state->piix3->dev.config[0x60 + i]) - pic_level |= irq_state->piix3->pci_irq_levels[i]; + if (pic_irq == piix3->dev.config[0x60 + i]) + pic_level |= piix3->pci_irq_levels[i]; } - qemu_set_irq(irq_state->pic[pic_irq], pic_level); + qemu_set_irq(piix3->pic[pic_irq], pic_level); } }