diff mbox

[U-Boot,04/18] ARM: zynq: Added efuse status register base address

Message ID b5bf45f6c33b4ed447b5277d74952f09d288610e.1398433337.git.michal.simek@xilinx.com
State Accepted
Delegated to: Michal Simek
Headers show

Commit Message

Michal Simek April 25, 2014, 1:42 p.m. UTC 
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

Added efuse status register base address. This register
is used for determining whether efuse was blown or not.
Also, added the zynq_get_silicon_version() to get the
silicon version of the zynq board.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv7/zynq/cpu.c              | 13 +++++++++++++
 arch/arm/include/asm/arch-zynq/hardware.h  |  9 +++++++++
 arch/arm/include/asm/arch-zynq/sys_proto.h |  1 +
 3 files changed, 23 insertions(+)

--
1.8.2.3
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 7626b5c..816d0c5 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -14,6 +14,9 @@  void lowlevel_init(void)
 {
 }

+#define ZYNQ_SILICON_VER_MASK	0xF0000000
+#define ZYNQ_SILICON_VER_SHIFT	28
+
 int arch_cpu_init(void)
 {
 	zynq_slcr_unlock();
@@ -42,6 +45,16 @@  int arch_cpu_init(void)
 	return 0;
 }

+unsigned int zynq_get_silicon_version(void)
+{
+	unsigned int ver;
+
+	ver = (readl(&devcfg_base->mctrl) &
+	       ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
+
+	return ver;
+}
+
 void reset_cpu(ulong addr)
 {
 	zynq_slcr_cpu_reset();
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index 39184da..20f62bf 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -22,6 +22,7 @@ 
 #define ZYNQ_SPI_BASEADDR0		0xE0006000
 #define ZYNQ_SPI_BASEADDR1		0xE0007000
 #define ZYNQ_DDRC_BASEADDR		0xF8006000
+#define ZYNQ_EFUSE_BASEADDR		0xF800D000

 /* Bootmode setting values */
 #define ZYNQ_BM_MASK		0xF
@@ -130,4 +131,12 @@  struct ddrc_regs {
 };
 #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)

+struct efuse_reg {
+	u32 reserved1[4];
+	u32 status;
+	u32 reserved2[3];
+};
+
+#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
+
 #endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index a68e1b3..2445a04 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -16,6 +16,7 @@  extern void zynq_slcr_devcfg_enable(void);
 extern u32 zynq_slcr_get_boot_mode(void);
 extern u32 zynq_slcr_get_idcode(void);
 extern void zynq_ddrc_init(void);
+extern unsigned int zynq_get_silicon_version(void);

 /* Driver extern functions */
 extern int zynq_sdhci_init(u32 regbase);